TDD PATTERN CONFIG C DL:2 UL:7 SUPPORT

[IbrahimBabiker87]

DO Srsran support TDD Pattern DL:2 UL:7 ?
If so what the suitable configuration for CSI

default config:

csi: 
     csi_rs_period: 80                       # Optional UINT (20). Sets the CSI-RS period in milliseconds. Supported: [10, 20, 40, 80].
     meas_csi_rs_slot_offset: 2              # Optional UINT (2). Sets the slot offset of first CSI-RS resource used for measurement.
     tracking_csi_rs_slot_offset: 12         # Optional UINT (12). Sets the slot offset of the first CSI-RS slot used for tracking.
     zp_csi_rs_slot_offset:                  # Optional TEXT. Sets the slot offset of the ZP CSI-RS resources.     
     pwr_ctrl_offset: 0                      # Optional INT (0). Sets the power offset of PDSCH RE to NZP CSI-RS RE in dB. Supported: [-8 - 15].

Error generated:

--== srsRAN gNB (commit 374200dee) ==--

Connecting to AMF on 10.0.135.40:38412
srsGNB FATAL ERROR: Failed to find valid csi-MeasConfig
Aborted

[herlesupreeth]

Could you please try the following configuration? NOTE: CSI-RS may collide with SSB/SIB1

meas_csi_rs_slot_offset: 1             # Optional UINT (2). Sets the slot offset of first CSI-RS resource used for measurement.
tracking_csi_rs_slot_offset: 11        # Optional UINT (12). Sets the slot offset of the first CSI-RS slot used for tracking.

I would rather recommend using TDD pattern DL:3 UL:6 and make sure to set minimum K1 and K2 as 3

[IbrahimBabiker87]

Below Error showed:

--== srsRAN gNB (commit 374200dee) ==--

Connecting to AMF on 10.0.135.40:38412
srsGNB ERROR: Unable to derive valid CSI-RS slot offsets and period for cell with pci=1

Aborted (core dumped)

[IbrahimBabiker87]

@herlesupreeth ,
When using 1 & 11 values suggested below error showed:

--== srsRAN gNB (commit 374200dee) ==--

Connecting to AMF on 10.0.135.40:38412
srsGNB ERROR: Unable to derive valid CSI-RS slot offsets and period for cell with pci=1

Aborted (core dumped)

[herlesupreeth]

Looks like its not possible with DL 2 UL 7 TDD pattern. You would have to use DL 3 and UL 6 TDD pattern.

I will investigate more on this and get back to you

[IbrahimBabiker87]

@herlesupreeth ,

This with 3:6 BTW

[herlesupreeth]

Strange, I am able to run with DL 3 and UL 6 TDD (Band 41).

Connecting to AMF on 172.22.0.10:38412
Available radio types: uhd and zmq.
Cell pci=1, bw=100 MHz, dl_arfcn=520002 (n41), dl_freq=2600.01 MHz, dl_ssb_arfcn=511950, ul_freq=2600.01 MHz

==== gNodeB started ===
Type <t> to view trace

And, I am setting only the TDD pattern as follows and leaving CSI-RS measurement config default

  tdd_ul_dl_cfg:
    nof_dl_slots: 3
    nof_dl_symbols: 0
    nof_ul_slots: 6

Can you try with above TDD pattern and leaving CSI-RS config as default?

[IbrahimBabiker87]

same issue even with default:

--== srsRAN gNB (commit 374200dee) ==--

Connecting to AMF on 10.0.135.40:38412
srsGNB ERROR: Unable to derive valid CSI-RS slot offsets and period for cell with pci=1

Aborted (core dumped)

cell_cfg:
  dl_arfcn: 650112                                              # ARFCN of the downlink carrier (center frequency).
  band: 77                                                        # The NR band.
  channel_bandwidth_MHz: 100                                       # Bandwith in MHz. Number of PRBs will be automatically derived.
  common_scs: 30                                                  # Subcarrier spacing in kHz used for data.
  plmn: "00101"                                                   # PLMN broadcasted by the gNB.
  tac: 1                                                          # Tracking area code (needs to match the core configuration).
  pci: 1                                                          # Physical cell ID. 
  nof_antennas_dl: 4                                              # Downlink number of antennas.
  nof_antennas_ul: 2                                              # Uplink number of anntennas.
  pcg_p_nr_fr1: +23                      # Optional INT (10). Sets the maximum total TX power to be used by the UE in this NR cell group across in FR1. Supported: [-30 - +23].
  tdd_ul_dl_cfg: 
    dl_ul_tx_period: 10                     # Optional INT (10). Sets the TDD pattern periodicity in slots. The combination of this value and the chosen numerology must lead to a TDD periodicity of 0.5, >
    nof_dl_slots: 3                         # Optional INT (6). Number of consecutive full Downlink slots. Supported: [0-80].
    nof_dl_symbols: 0                       # Optional INT (0). Number of Downlink symbols at the beginning of the slot following full Downlink slots. Supported: [0-13].
    nof_ul_slots: 6                         # Optional INT (3). Number of consecutive full Uplink slots. Supported: [0 - 80].
    nof_ul_symbols: 0                       # Optional INT (0). Number of Uplink symbols at the end of the slot preceding the first full Uplink slot. Supported: [0-13].

 csi: 
#     csi_rs_enabled: true                       # Optional BOOLEAN (1). Enables CSI-RS resources and CSI reporting. Supported: [0, 1].
#     csi_rs_period: 20                       # Optional UINT (20). Sets the CSI-RS period in milliseconds. Supported: [10, 20, 40, 80].
     meas_csi_rs_slot_offset: 2              # Optional UINT (2). Sets the slot offset of first CSI-RS resource used for measurement.
     tracking_csi_rs_slot_offset: 12            # Optional UINT (12). Sets the slot offset of the first CSI-RS slot used for tracking.
#     zp_csi_rs_slot_offset:                  # Optional TEXT. Sets the slot offset of the ZP CSI-RS resources.     
#     pwr_ctrl_offset: 0                      # Optional INT (0). Sets the power offset of PDSCH RE to NZP CSI-RS RE in dB. Supported: [-8 - 15].

[herlesupreeth]

Hey, please leave the csi section in config commented out. The slot offset would be automatically calculated based on the TDD pattern used

[herlesupreeth]

Btw, you can test TDD pattern DL:2 UL:7 with the following configuration. NOTE: Leave CSI configuration default (i.e. not configured)

  tdd_ul_dl_cfg:
    dl_ul_tx_period: 10
    nof_dl_slots: 2
    nof_dl_symbols: 9
    nof_ul_slots: 7
    nof_ul_symbols: 0

[frankist]

Can you test again with https://github.com/srsran/srsRAN_Project/tree/test ? commit hash: 342df75

[IbrahimBabiker87]

Currently the srsgnb only supports one UL-PDCCH per UE per slot. This leads to the under utilization of the PUSCH if the cell has more UL slots than DL slots, and only one UE with data to schedule. We will revisit this limitation in future releases.

is this still the case ???

[herlesupreeth]

No. When the TDD pattern has more UL slots than DL slots then we allow more than one UL PDCCH per UE per slot

[herlesupreeth]

You can refer here - #668

[IbrahimBabiker87]

@herlesupreeth

will it work with TDD pattern DSUUUUDSUU ??

as Im seeing max throughput of 171Mbps.

and UL grants is limited to slots 2,3,8,9 & 12,13,18,19 , k2= 2

pci rnti | cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  rsrp  mcs  brate   ok  nok  (%)    bsr     ta  phr
   3 4601 |  14 4.0   22   395k  100    1   0%      0 |  27.9 -16.2   28   171M  800    0   0%   300k   122n   17
   3 4601 |  14 4.0   22   392k  100    1   0%      0 |  27.4 -16.1   28   171M  800    1   0%   300k   105n   18
   3 4601 |  14 4.0   22   403k  100    1   0%      0 |  28.2 -16.3   28   171M  800    0   0%   300k    89n   18
   3 4601 |  14 4.0   22   400k  100    1   0%      0 |  28.2 -16.3   28   171M  800    0   0%   300k   122n   18
   3 4601 |  14 4.0   22   390k  100    1   0%      0 |  28.2 -16.3   28   171M  800    0   0%  1.06M   105n   18
   3 4601 |  14 4.0   22   391k  100    2   1%      0 |  28.2 -16.3   28   171M  800    1   0%   300k   138n   18
   3 4601 |  14 4.0   22   390k  100    0   0%      0 |  28.2 -16.3   28   171M  800    0   0%   300k   113n   18
   3 4601 |  14 4.0   23   410k  100    1   0%      0 |  28.2 -16.3   28   171M  800    0   0%   300k    97n   18
   3 4601 |  14 4.0   22   399k  100    1   0%      0 |  28.2 -16.3   28   171M  800    2   0%   300k   130n   18
   3 4601 |  14 4.0   22   392k  100    2   1%      0 |  28.2 -16.3   28   171M  800    0   0%   300k   113n   18
   3 4601 |  14 4.0   22   390k  100    0   0%      0 |  28.2 -16.3   28   171M  800    0   0%   300k    97n   18

2024-08-07T10:26:42.468024 [SCHED   ] [I] [   383.2] Slot decisions pci=3 t=3us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=4 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.468515 [SCHED   ] [I] [   383.3] Slot decisions pci=3 t=2us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=2 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.471016 [SCHED   ] [I] [   383.8] Slot decisions pci=3 t=1us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=1 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.471517 [SCHED   ] [I] [   383.9] Slot decisions pci=3 t=1us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=0 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.473023 [SCHED   ] [I] [  383.12] Slot decisions pci=3 t=3us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=3 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.473522 [SCHED   ] [I] [  383.13] Slot decisions pci=3 t=2us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=2 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.476010 [SCHED   ] [I] [  383.18] Slot decisions pci=3 t=2us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=1 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2
2024-08-07T10:26:42.476523 [SCHED   ] [I] [  383.19] Slot decisions pci=3 t=1us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=0 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=26647 k2=2

[herlesupreeth]

will it work with TDD pattern DSUUUUDSUU ??

havent tried with this TDD pattern

and UL grants is limited to slots 2,3,8,9 & 12,13,18,19 , k2= 2

looks like no more than 1 UL PDCCH per UE per slot. Can you please share the gNB log and the configuration file you are using?

[IbrahimBabiker87]

gnb.zip
test_config_full.zip
@herlesupreeth
here you go

[herlesupreeth]

looks like no more than 1 UL PDCCH per UE per slot.

My bad. This is incorrect what I said above because upon grepping the logs you attached I see that multiple k2 values are used. This means we are scheduling more than 1 UL PDCCH per UE per slot. So, thats the maximum throughput you can achieve in UL

 1832253: 2024-08-07T11:23:40.843514 [SCHED   ] [I] [  204.12] Slot decisions pci=1 t=3us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=1 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=24597 k2=6
 1832254: 2024-08-07T11:23:40.844015 [SCHED   ] [I] [  204.13] Slot decisions pci=1 t=3us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=4 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=24597 k2=6
 1832255: 2024-08-07T11:23:40.844519 [SCHED   ] [I] [  204.14] Slot decisions pci=1 t=2us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=2 ss_id=2 rb=[3..271) newtx=false rv=0 tbs=24597 k2=4
 1832256: 2024-08-07T11:23:40.845017 [SCHED   ] [I] [  204.15] Slot decisions pci=1 t=2us (0 PDSCHs, 1 PUSCH): UL: ue=0 rnti=0x4601 h_id=8 ss_id=2 rb=[3..271) newtx=true rv=0 tbs=24597 k2=5

[IbrahimBabiker87]

@frankist
Same issue observed with test commit= c4930b7
here with more degradation in overall UL throughput

ad@bm-super4:~/srsRAN_Project/configs$ sudo gnb -c cell_config.yml 

The PRACH detector will not meet the performance requirements with the configuration {Format 0, ZCZ 0, SCS 1.25kHz, Rx ports 1}.
EAL: Detected CPU lcores: 32
EAL: Detected NUMA nodes: 1
EAL: Detected shared linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: 2048 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
EAL: Probe PCI driver: net_i40e (8086:1572) device: 0000:01:00.0 (socket -1)
TELEMETRY: No legacy callbacks, legacy socket not created

--== srsRAN gNB (commit c4930b75b) ==--

Connecting to AMF on 10.0.135.40:38412
Initializing the Open Fronthaul Interface for sector#0: ul_compr=[BFP,9], dl_compr=[BFP,9], prach_compr=[BFP,9], prach_cp_enabled=false, downlink_broadcast=false
tWarning: Configured PRACH occasion collides with PUCCH RBs ([0..1) intersects [0..3)). Some interference between PUCCH and PRACH is expected.
Warning: Configured PRACH occasion collides with PUCCH RBs ([0..1) intersects [0..3)). Some interference between PUCCH and PRACH is expected.
Cell pci=1, bw=100 MHz, dl_arfcn=623334 (n78), dl_freq=3350.01 MHz, dl_ssb_arfcn=620640, ul_freq=3350.01 MHz

==== gNodeB started ===
Type <t> to view trace

         -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28    97M  457  343  42%   300k
  1 4604   15   4   22   3.9k    1    0   0%      0 |  30.4   28    95M  445  355  44%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28    98M  463  337  42%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28    89M  417  382  47%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28    82M  385  416  51%   300k
  1 4604   14   4    0      0    0    0   0%      0 |  29.6   28    86M  404  396  49%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.7   28    86M  402  398  49%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.2   28    90M  424  376  47%   300k
  1 4604   15   4   22    26k    8    0   0%      0 |  29.7   28    77M  361  439  54%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.2   28    86M  403  397  49%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28    91M  429  371  46%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4   22   3.1k    1    0   0%      0 |  30.0   28    82M  383  417  52%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  30.7   28    99M  463  337  42%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.7   28   100M  467  332  41%   300k
  1 4604   14   4    0      0    0    0   0%      0 |  30.4   28    90M  422  379  47%   300k
  1 4604   15   4   22    22k    7    0   0%      0 |  31.3   28   109M  513  287  35%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  31.1   28    93M  435  365  45%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.9   28   103M  484  316  39%   300k
  1 4604   15   4   22    26k    7    1  12%      0 |  30.8   28   100M  470  330  41%   300k
  1 4604   15   4   22    40k   10    0   0%      0 |  30.6   28    85M  397  403  50%   300k
  1 4604   15   4   20   118k    6    0   0%      0 |  30.9   28    84M  395  405  50%   300k
  1 4604   15   4   22    34k    9    0   0%      0 |  30.9   28    74M  346  454  56%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  30.8   28    84M  392  408  51%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  31.7   28   111M  520  280  35%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  31.3   28    91M  428  372  46%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  31.6   28   108M  508  292  36%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.3   28   134M  629  171  21%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   145M  680  120  15%   300k
  1 4604   15   4   22    32k    9    0   0%      0 |  29.3   28   121M  566  234  29%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  31.9   28   121M  568  232  29%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.0   28   108M  505  295  36%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  28.4   28   103M  484  316  39%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  28.4   28    98M  460  340  42%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   120M  564  236  29%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.5   28   124M  582  218  27%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.7   28   143M  669  131  16%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.3   28   136M  638  162  20%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   135M  631  169  21%   300k
  1 4604   15   4   22    27k    8    0   0%      0 |  29.9   28   132M  620  180  22%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   133M  622  178  22%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   135M  634  166  20%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  30.1   28   136M  639  161  20%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   136M  638  162  20%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   135M  633  167  20%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   141M  662  138  17%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   130M  612  188  23%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   137M  642  158  19%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   132M  617  183  22%   300k
  1 4604   15   4   22    32k   10    0   0%      0 |  30.2   28   129M  604  196  24%   300k
  1 4604   15   4   22    19k    6    0   0%      0 |  30.2   28   124M  580  220  27%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   126M  592  208  26%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  29.9   28   127M  595  205  25%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   129M  606  194  24%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.1   28   128M  600  200  25%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   125M  585  215  26%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   125M  588  212  26%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   127M  597  203  25%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   127M  594  206  25%   300k
  1 4604   15   4   22    24k    7    0   0%      0 |  30.0   28   123M  578  222  27%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   129M  604  196  24%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28   125M  586  214  26%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  29.9   28   126M  593  207  25%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   126M  593  207  25%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.7   28   121M  566  234  29%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.5   28   129M  603  197  24%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   123M  579  221  27%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28   126M  590  210  26%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.7   28   127M  594  206  25%   300k
  1 4604   15   4   22    23k    7    0   0%      0 |  29.8   28   126M  591  209  26%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   127M  597  203  25%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   125M  588  212  26%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  30.0   28   122M  573  227  28%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   123M  577  223  27%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28   125M  588  212  26%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28   125M  586  214  26%   300k
  1 4605   14   4   22    22k    6    0   0%      0 |  29.5   22    14k    3    0   0%      0
  1 4604   15   4    0      0    0    0   0%      0 |  29.3   28   124M  585  215  26%   300k
  1 4605   14   4   25   471k   73    5   6%      0 |  24.1   28   282k   40   12  23%      0
  1 4604   15   4    0      0    0    0   0%      0 |  29.6   28   120M  568  231  28%   300k
  1 4605   15   4   24   1.5M  186    8   4%      0 |  20.8   27   1.0M   84   29  25%      0

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  30.0   28   124M  583  212  26%   300k
  1 4605   14   4   23   228k   35    3   7%      0 |  19.1   28   353k   23   12  34%      0
  1 4604   15   4   22    27k    8    0   0%      0 |  29.5   28   115M  546  223  28%   300k
  1 4605   14   4   23   507k   91    0   0%      0 |  15.2   21   1.3M   80   43  34%    745
  1 4604   15   4    0      0    0    0   0%      0 |  29.5   28    56M  263  288  52%   300k
  1 4605   15   4   22   1.5M  117    8   6%      0 |   6.8    8   5.2M  247   38  13%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.3   28    15M   71  329  82%   300k
  1 4605   14   4   22   198k   38    0   0%      0 |   4.8    5   8.2M  358   42  10%   300k
  1 4604   15   4   22   9.3k    3    0   0%      0 |  29.5   28    11M   51  349  87%   300k
  1 4605   15   4   22   151k   23    0   0%      0 |   5.0    5   8.1M  350   50  12%   300k
  1 4604   15   4   22   7.8k    2    0   0%      0 |  29.5   28    13M   61  340  84%   300k
  1 4605   14   4   21    85k   17    0   0%      0 |   5.0    5   8.0M  340   59  14%   300k
  1 4604   15   4   22   3.1k    1    0   0%      0 |  29.7   28   9.6M   45  355  88%   300k
  1 4605   14   4   22    62k   12    0   0%      0 |   5.1    5   8.4M  352   48  12%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   7.2M   34  365  91%   300k
  1 4605   15   4   22   222k   26    0   0%      0 |   4.9    5   8.4M  354   47  11%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28    11M   53  347  86%   300k
  1 4605   14   4   22   510k   46    0   0%      0 |   5.0    5   8.0M  343   57  14%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   8.7M   41  355  89%   300k
  1 4605   14   4   22   189k   28    0   0%      0 |   5.0    6   8.1M  342   62  15%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.9   28   9.6M   45  355  88%   300k
  1 4605   15   4   22   517k   51    0   0%      0 |   4.9    5   8.1M  350   50  12%   300k

          -----------------DL-----------------------|------------------UL--------------------
pci rnti  cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  mcs  brate   ok  nok  (%)    bsr
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   5.8M   27  373  93%   300k
  1 4605   14   4   22   181k   23    0   0%      0 |   4.8    5   8.2M  353   47  11%   300k
  1 4604   15   4   22   6.2k    2    0   0%      0 |  29.7   28   4.3M   20  380  95%   300k
  1 4605   14   4   23    33k    8    0   0%      0 |   4.9    5   8.2M  348   52  13%   300k
  1 4604   15   4   21   3.0k    1    0   0%      0 |  29.8   28   3.0M   14  387  96%   300k
  1 4605   15   4   22    72k    8    0   0%      0 |   4.9    5   8.4M  364   35   8%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   2.8M   13  387  96%   300k
  1 4605   15   4   21    39k   10    0   0%      0 |   5.0    5   8.2M  346   54  13%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   5.5M   26  376  93%   300k
  1 4605   15   4   21   316k   36    0   0%      0 |   5.1    5   8.2M  347   51  12%   300k
  1 4604   15   4    0      0    0    0   0%      0 |  29.8   28   2.6M   12  388  97%   300k
  1 4605   15   4   22   178k   26    0   0%      0 |   4.8    5   8.5M  370   30   7%   300k
  1 4606   15   2   23    16k    7    0   0%      0 |  28.7   28    24k    8   50  86%   413k
  1 4605   14   4   22    13k    4    0   0%      0 |   4.6    4    11M  501   23   4%   300k
  1 4605   15   4   22   6.3k    2    0   0%      0 |   4.5    5    11M  498   18   3%   300k
  1 4607   15   1   18   9.5k    5    0   0%      0 |  26.3   22    14k    3    0   0%      0
  1 4605   15   4   23   294k   33    0   0%      0 |   4.8    5    18M  763   37   4%   300k
  1 4607   15   1    0      0    0    0   0%      0 |   n/a    0      0    0    0   0%      0
^CStopping ..
DPDK - Closing port_id '0' ... Done