Understanding TDD Slot Configuration

[lmcclennan]

Using the default TDD slot configuration as follows:

 tdd_ul_dl_cfg: 
    dl_ul_tx_period: 10                     
    nof_dl_slots: 6                        
    nof_dl_symbols: 8                       
    nof_ul_slots: 3                         
    nof_ul_symbols: 0

results in a TDD control signal that doesn't make sense to me. This is a signal generated by a USRP X410 that is used to control the front end RF switch of the gnodeb and switch from Tx mode to Rx mode. When the signal is high the USRP is in Tx mode (DL) and when the signal is low the USRP is in Rx mode (UL). Given than the SCS is 30 kHz and therefore a slot is 0.5 ms long, I would expect this signal to be periodic every 5 ms with DL mode being at least 3 ms in length followed by UL mode of at least 1.5 ms. I'm not sure what to expect for the "S" slot, maybe DL mode since the number of DL symbols is set to 8. Clearly, that is not what is seen in the image.

Can anyone explain why the TDD control signal looks the way it does given the slot configuration? Thanks
,

[frankist]

Are you pushing enough traffic in the DL direction?

Try running the gnb first in test mode. Relevant configs:

test_mode:
  test_ue:
    rnti: 0x4444

amf:
  no_core: true

This will automatically fill the DL and UL resource grids with fake traffic