Available DL/UL slot configuration: srsran_project

[praghur]

Hello all.

I am using x310 as gNB for my OTA experiment. Please see attached the configuration file for this gNB. In my system containing 2 gNBs - each connected to 1 UE, I want to achieve low latency communication between two UEs via CN. The path taken by a data packet in this communication would be:
Source UE --> gNB1 --> CN --> gnb2 --> Destination UE.

In this case to achieve low latency, I was thinking of using a slot format with approximately equal distribution of DL and UL slots. The low_latency.yaml file in srsran_project provides a configuration that has more number of DL slots compared to UL slots.
tdd_ul_dl_cfg:
dl_ul_tx_period: 4
nof_dl_slots: 2
nof_dl_symbols: 10
nof_ul_slots: 1
nof_ul_symbols: 0

I am unable to understand how to configure this slot format to improve the resource availability in both DL and UL direction. For example, the configuration shown below works:
tdd_ul_dl_cfg:
dl_ul_tx_period: 4
nof_dl_slots: 1
nof_dl_symbols: 0
nof_ul_slots: 1
nof_ul_symbols: 13

But the following configuration does not work:
tdd_ul_dl_cfg:
dl_ul_tx_period: 3 --> Any change to the period gives an error
nof_dl_slots: 1
nof_dl_symbols: 0
nof_ul_slots: 1
nof_ul_symbols: 0

The error obtained is provided below:

--== srsRAN gNB (commit 4ac5300) ==--

The PRACH detector will not meet the performance requirements with the configuration {Format B4, ZCZ 0, SCS 30kHz, Rx ports 1}.
Lower PHY in quad executor mode.
N2: Connection to AMF on 192.168.1.1:38412 completed
srsRAN FATAL ERROR: Failed to find valid csi-MeasConfig
Aborted

Is there a way to understand which of the slot format could be available for use in srsran_project? Also, is there a list of available DL/UL slot configuration for srsran?

Thanks a lot in advance.
gnb_x310_1.txt

[herlesupreeth]

As per spec you can use any TDD pattern as long as the TDD period of pattern 1 + TDD period of pattern 2 divides 20 msec. So in your case TDD period (pattern 1) of 3 slots == 1.5 msec and it does not divide 20 msec. Also, another thing to consider when settings TDD configuration is that there should be enough (atleast 3) DL slots for CSI-RS to be sent.

[praghur]

Thanks a lot, Supreeth. This was tremendously helpful. I read your response and went into the theory behind each of these concepts to understand. I had 2 follow-up questions:

1. The srsran documentation provides pattern1 and pattern2 for DL/UL slot configuration. SCS = 30 kHz

tdd_ul_dl_cfg: 
    dl_ul_tx_period: 10                    
    nof_dl_slots: 6                        
    nof_dl_symbols: 8                       
    nof_ul_slots: 3                         
    nof_ul_symbols: 0                       
    pattern2: 
      dl_ul_tx_period: 10                       
      nof_dl_slots: 6                          
      nof_dl_symbols: 8                        
      nof_ul_slots: 3                           
      nof_ul_symbols: 0

In my gNB configuration file, if I do not specify pattern2, would it take the default pattern2 mentioned in the srsran documentation or would it only configure the gNB with pattern1? Since I am working on a latency-strict application, is it necessary to change both pattern1 and patthern2 configuration to achieve lower latency?

 tdd_ul_dl_cfg: 
   dl_ul_tx_period: 4
    nof_dl_slots: 2
    nof_dl_symbols: 10
    nof_ul_slots: 1
    nof_ul_symbols: 0
    pattern2: 
      dl_ul_tx_period: 6
      nof_dl_slots: 2
      nof_dl_symbols: 10
      nof_ul_slots: 3
      nof_ul_symbols: 0

2. The information about needing at least 3 DL slots was really useful. I was not aware of this requirement. I am curious to know if this is specific to srsran or is it being driven by any standard?

Thanks a lot once again 😀

[herlesupreeth]

In my gNB configuration file, if I do not specify pattern2, would it take the default pattern2 mentioned in the srsran documentation or would it only configure the gNB with pattern1?

Only pattern1 is configured

Since I am working on a latency-strict application, is it necessary to change both pattern1 and patthern2 configuration to achieve lower latency?

No, its not a strict requirement

The information about needing at least 3 DL slots was really useful. I was not aware of this requirement. I am curious to know if this is specific to srsran or is it being driven by any standard?

Partially specific to srsran (since we support only periodic CSI-RS and reporting) and partially due to standard. Because the spec states that CSI-RS for tracking needs to be in consecutive DL slots.