Underflow/Overflow

[houshangaziziaccelleran]

Hello
What are the possible causes of following type of errors:

Late: 0; Underflow: 69; Overflow: 0;
Late: 0; Underflow: 134; Overflow: 0;
Late: 0; Underflow: 222; Overflow: 0;
Late: 0; Underflow: 275; Overflow: 0;

I am using srsRAN with n310 radio. No issue with the host machine running srsRAN (powerful enough and I am using CPU isolation).
I am experiencing this when I do Downlink Data.
Here is the expect_execution of my config file:

expert_execution:
  cell_affinities:
    -
      l1_dl_cpus: 23,24,55,56,28,29,60,61
      l1_ul_cpus: 23,24,55,56,28,29,60,61
      l1_dl_pinning: mask
      l1_ul_pinning: mask
      l2_cell_cpus: 25,57,30,62
      l2_cell_pinning: mask
      ru_cpus: 26,58,31,63
      ru_pinning: mask
  affinities:
    low_priority_cpus: 23,24,55,56,28,29,60,61
    low_priority_pinning: mask
    ru_timing_cpu: 22,54,27,59
    ofh:
      - ru_txrx_cpus: 26,58,31,63
  threads:
    non_rt:
      nof_non_rt_threads: 4
    upper_phy:
      pdsch_processor_type: auto
      nof_pusch_decoder_threads: 6
      nof_ul_threads: 12
      nof_dl_threads: 6
    lower_phy:
      execution_profile: quad
    ofh:
      enable_dl_parallelization: true

[robertfalkenberg]

Can you share the ru_sdr section from your config?

[houshangaziziaccelleran]

Hi @robertfalkenberg

ru_sdr:
  srate: 122.88
  device_driver: uhd
  device_args: >
    use_dpdk=0,
    type=n3xx,
    mgmt_addr=10.10.0.100,
    product=n310,
    clock_source=internal,
    time_source=internal,
    addr=10.10.1.100,
    second_addr=10.10.2.100,
    master_clock_rate=122.88e6,
    send_frame_size=8500,
    recv_frame_size=8500

[robertfalkenberg]

Adjusting the UHD settings for high bandwidths with USRPs is a bit tricky.

The best I can provide is following settings for 50MHz TDD tests with srate 92.16 on X300 with reasonable amount of underflows:

ru_sdr:
  srate: 92.16

  device_driver: uhd
  device_args: type=x300,type=x300,addr=192.168.30.122,send_frame_size=8000,recv_frame_size=8000
  tx_gain: 25
  rx_gain: 20

  lo_offset: 20

  clock: external

  sync: external
  time_alignment_calibration: auto

   1 4601 |  14 1.0   20   126M 1512   27   1%   567k |  27.9  -9.8   26   258k   81   10  10%      0   355n   26
   1 4601 |  14 1.0   19   124M 1548    0   0%   852k |  30.4  -9.6   27   243k   50    0   0%      0   284n   26

          |--------------------DL---------------------|-------------------------UL------------------------------
 pci rnti | cqi  ri  mcs  brate   ok  nok  (%)  dl_bs | pusch  rsrp  mcs  brate   ok  nok  (%)    bsr     ta  phr
   1 4601 |  14 1.0   22   141M 1548    0   0%   866k |  30.9  -9.6   27   243k   50    0   0%      0   214n   26
Late: 0; Underflow: 1; Overflow: 0;
   1 4601 |  14 1.0   22   140M 1532   17   1%   869k |  31.0  -9.6   27   238k   49    0   0%      0   212n   26
Late: 0; Underflow: 1; Overflow: 0;