Support audio reset in reset controller driver for Starfive JH7100 SOC

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>

Author: WalkerChenL

arch/riscv/boot/dts/starfive/jh7100.dtsi

@@ -295,11 +295,17 @@
 		};
 
 		rstgen: reset-controller@11840000 {
-			compatible = "starfive,jh7100-reset";
+			compatible = "starfive,jh7100-reset", "syscon";
 			reg = <0x0 0x11840000 0x0 0x10000>;
 			#reset-cells = <1>;
 		};
 
+		audrst: reset-controller@10490000 {
+			compatible = "starfive,jh7100-reset-audio", "syscon";
+			reg = <0x0 0x10490000 0x0 0x10000>;
+			#reset-cells = <1>;
+		};
+
 		qspi: spi@11860000 {
 			compatible = "cdns,qspi-nor";
 			reg = <0x0 0x11860000 0x0 0x10000>,

drivers/reset/reset-starfive-jh7100.c

@@ -3,12 +3,14 @@
  * Reset driver for the StarFive JH7100 SoC
  *
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2021 Walker Chen <walker.chen@starfivetech.com>
  */
 
 #include <linux/bitmap.h>
 #include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
 #include <linux/spinlock.h>
@@ -25,36 +27,30 @@
 #define JH7100_RESET_STATUS2	0x18
 #define JH7100_RESET_STATUS3	0x1c
 
-#if BITS_PER_LONG == 64
-#define jh7100_reset_read	readq
-#define jh7100_reset_write	writeq
-#else
-#define jh7100_reset_read	readl
-#define jh7100_reset_write	writel
-#endif
+#define JH7100_AUDIO_RESET_STATUS0 	0x4
 
-/*
- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
- * line 32m + n, and writing a 0 deasserts the same line.
- * Most reset lines have their status inverted so a 0 bit in the STATUS
- * register means the line is asserted and a 1 means it's deasserted. A few
- * lines don't though, so store the expected value of the status registers when
- * all lines are asserted.
- */
-static const DECLARE_BITMAP(jh7100_reset_asserted, 4 * 32) = {
-	BITMAP_FROM_U64(BIT_ULL_MASK(JH7100_RST_U74) |
-			BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
-			BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
-			BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
-			BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET)),
-	BITMAP_FROM_U64(BIT_ULL_MASK(JH7100_RST_E24)),
+enum jh7100_reset_ctrl_type {
+	PERIPHERAL = 0,
+	AUDIO,
+	ISP,
+};
+
+static const u32 jh7100_reset_asserted[4] = {
+	BIT(JH7100_RST_U74 % 32) |
+	BIT(JH7100_RST_VP6_DRESET % 32) |
+	BIT(JH7100_RST_VP6_BRESET % 32),
+
+	BIT(JH7100_RST_HIFI4_DRESET % 32) |
+	BIT(JH7100_RST_HIFI4_BRESET % 32),
+
+	BIT_MASK(JH7100_RST_E24	% 32)
 };
 
 struct jh7100_reset {
 	struct reset_controller_dev rcdev;
 	/* protect registers against concurrent read-modify-write */
 	spinlock_t lock;
-	void __iomem *base;
+	struct regmap *regmap;
 };
 
 static inline struct jh7100_reset *
@@ -63,106 +59,178 @@ jh7100_reset_from(struct reset_controller_dev *rcdev)
 	return container_of(rcdev, struct jh7100_reset, rcdev);
 }
 
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
-			       unsigned long id, bool assert)
+static int jh7100_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
+				unsigned int reg_status, bool assert)
 {
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
-	unsigned long offset = id / BITS_PER_LONG;
-	void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(long);
-	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(long);
-	unsigned long mask = BIT_MASK(id);
-	unsigned long done = jh7100_reset_asserted[offset] & mask;
-	unsigned long value;
+	unsigned long bank = id / 32;
+	u32 offset = JH7100_RESET_ASSERT0 + 4 * bank;
+	u32 status = reg_status + 4 * bank;
+	u32 mask = BIT(id % 32);
+	u32 done = jh7100_reset_asserted[bank] & mask;
 	unsigned long flags;
-	int ret;
+	unsigned long timeout;
+	u32 value = 0;
+	int ret = 0;
 
 	if (!assert)
 		done ^= mask;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	value = jh7100_reset_read(reg_assert);
+	regmap_read(data->regmap, offset, &value);
 	if (assert)
 		value |= mask;
 	else
 		value &= ~mask;
-	jh7100_reset_write(value, reg_assert);
+	regmap_write(data->regmap, offset, value);
 
-	/* if the associated clock is gated, deasserting might otherwise hang forever */
-	ret = readx_poll_timeout_atomic(jh7100_reset_read, reg_status, value,
-				        (value & mask) == done, 0, 1000);
+	timeout = jiffies + msecs_to_jiffies(10);
+	do {
+		regmap_read(data->regmap, status, &value);
+		if (time_after(jiffies, timeout)) {
+			ret = -ETIMEDOUT;
+			break;
+		}	
+	} while ((value & mask) != done);
 
 	spin_unlock_irqrestore(&data->lock, flags);
 	return ret;
 }
 
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
+static int jh7100_periph_reset_assert(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, true);
+	return jh7100_reset_update(rcdev, id, JH7100_RESET_STATUS0, true);
 }
 
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
+static int jh7100_periph_reset_deassert(struct reset_controller_dev *rcdev,
 				 unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, false);
+	return jh7100_reset_update(rcdev, id, JH7100_RESET_STATUS0, false);
 }
 
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
+static int jh7100_periph_reset_reset(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
-	int ret;
-
-	ret = jh7100_reset_assert(rcdev, id);
+	int ret = jh7100_periph_reset_assert(rcdev, id);
 	if (ret)
 		return ret;
 
-	return jh7100_reset_deassert(rcdev, id);
+	return jh7100_periph_reset_deassert(rcdev, id);
 }
 
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
-			       unsigned long id)
+static int jh7100_get_reset_status(struct reset_controller_dev *rcdev,
+					unsigned int reg_status,
+					unsigned long id)
 {
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
-	unsigned long offset = id / BITS_PER_LONG;
-	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(long);
-	unsigned long value = jh7100_reset_read(reg_status);
-	unsigned long mask = BIT_MASK(id);
+	unsigned long bank = id / 32;
+	unsigned long mask = BIT(id % 32);
+	u32 value = 0;
+
+	reg_status = reg_status + 4 * bank;
+	regmap_read(data->regmap, reg_status, &value);
 
-	return !((value ^ jh7100_reset_asserted[offset]) & mask);
+	return  !((value ^ jh7100_reset_asserted[bank]) & mask);
 }
 
-static const struct reset_control_ops jh7100_reset_ops = {
-	.assert		= jh7100_reset_assert,
-	.deassert	= jh7100_reset_deassert,
-	.reset		= jh7100_reset_reset,
-	.status		= jh7100_reset_status,
+static int jh7100_periph_reset_status(struct reset_controller_dev *rcdev,
+					unsigned long id)
+{
+	return jh7100_get_reset_status(rcdev, JH7100_RESET_STATUS0, id);
+}
+
+static const struct reset_control_ops jh7100_periph_reset_ops = {
+	.assert		= jh7100_periph_reset_assert,
+	.deassert	= jh7100_periph_reset_deassert,
+	.reset		= jh7100_periph_reset_reset,
+	.status		= jh7100_periph_reset_status,
+};
+
+static int jh7100_audio_reset_assert(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	return jh7100_reset_update(rcdev, id, JH7100_AUDIO_RESET_STATUS0, true);
+}
+
+static int jh7100_audio_reset_deassert(struct reset_controller_dev *rcdev,
+				 unsigned long id)
+{
+	return jh7100_reset_update(rcdev, id, JH7100_AUDIO_RESET_STATUS0, false);
+}
+
+static int jh7100_audio_reset_reset(struct reset_controller_dev *rcdev,
+					unsigned long id)
+{
+	int ret = jh7100_audio_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
+
+	return jh7100_audio_reset_deassert(rcdev, id);
+}
+
+static int jh7100_audio_reset_status(struct reset_controller_dev *rcdev,
+					unsigned long id)
+{
+	return jh7100_get_reset_status(rcdev, JH7100_AUDIO_RESET_STATUS0, id);
+}
+
+static const struct reset_control_ops jh7100_audio_reset_ops = {
+	.assert		= jh7100_audio_reset_assert,
+	.deassert	= jh7100_audio_reset_deassert,
+	.reset		= jh7100_audio_reset_reset,
+	.status		= jh7100_audio_reset_status,
 };
 
 static int __init jh7100_reset_probe(struct platform_device *pdev)
 {
+	enum jh7100_reset_ctrl_type type;
+	struct regmap *regmap;
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
 	struct jh7100_reset *data;
 
 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 
-	data->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(data->base))
-		return PTR_ERR(data->base);
+	type = (enum jh7100_reset_ctrl_type)of_device_get_match_data(dev);
 
-	data->rcdev.ops = &jh7100_reset_ops;
+	regmap = syscon_node_to_regmap(np);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "failed to get reset controller regmap\n");
+		return PTR_ERR(regmap);
+	}
+
+	data->regmap = regmap;
+	data->rcdev.of_node = np;
+	data->rcdev.dev = dev;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = JH7100_RSTN_END;
-	data->rcdev.dev = &pdev->dev;
-	data->rcdev.of_node = pdev->dev.of_node;
+	if (type == PERIPHERAL) {
+		data->rcdev.ops = &jh7100_periph_reset_ops;
+		data->rcdev.nr_resets = JH7100_RSTN_END;
+	} else if (type == AUDIO) {
+		data->rcdev.ops = &jh7100_audio_reset_ops;
+		data->rcdev.nr_resets = JH7100_AUDIO_RSTN_END;
+	} else {
+		;
+	} 
+
 	spin_lock_init(&data->lock);
 
 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
 }
 
 static const struct of_device_id jh7100_reset_dt_ids[] = {
-	{ .compatible = "starfive,jh7100-reset" },
+	{
+		.compatible = "starfive,jh7100-reset",
+		.data = (void *)PERIPHERAL,
+	},
+	{
+		.compatible = "starfive,jh7100-reset-audio",
+		.data = (void *)AUDIO,
+	},
 	{ /* sentinel */ }
 };
 

include/dt-bindings/clock/starfive-jh7100.h

@@ -199,4 +199,41 @@
 
 #define JH7100_CLK_END			189
 
+/* audio */
+#define JH7100_CLK_ADC_MCLK		0
+#define JH7100_CLK_I2S1_MCLK 		1
+#define JH7100_CLK_APB_I2SADC 		2
+#define JH7100_CLK_I2SADC_BCLK 		3
+#define JH7100_CLK_I2SADC_BCLK_INV 	4
+#define JH7100_CLK_I2SADC_LRCLK 	5
+#define JH7100_CLK_APB_PDM 		6
+#define JH7100_CLK_PDM_MCLK 		7
+#define JH7100_CLK_APB_I2SVAD 		8
+#define JH7100_CLK_SPDIF 		9
+#define JH7100_CLK_APB_SPDIF 		10
+#define JH7100_CLK_APB_PWMDAC 		11
+#define JH7100_CLK_DAC_MCLK 		12
+#define JH7100_CLK_APB_I2S0 		13
+#define JH7100_CLK_I2S0_BCLK 		14
+#define JH7100_CLK_I2S0_BCLK_INV 	15
+#define JH7100_CLK_I2S0_LRCLK 		16
+#define JH7100_CLK_APB_I2S1 		17
+#define JH7100_CLK_I2S1_BCLK 		18
+#define JH7100_CLK_I2S1_BCLK_INV 	19
+#define JH7100_CLK_I2S1_LRCLK 		20
+#define JH7100_CLK_APB_I2SDAC16K 	21
+#define JH7100_CLK_APB0_BUS 		22
+#define JH7100_CLK_DMA1P_AHB 		23
+#define JH7100_CLK_APB_USB 		24
+#define JH7100_CLK_USB_LPM 		25
+#define JH7100_CLK_USB_STB 		26
+
+#define JH7100_CLK_ADC_BCLK_IOPAD 	27
+#define JH7100_CLK_ADC_LRCLK_IOPAD	28
+#define JH7100_CLK_DAC_BCLK_IOPAD 	29
+#define JH7100_CLK_DAC_LRCLK_IOPAD 	30
+#define JH7100_CLK_CODEC_EXT 		31
+#define JH7100_CLK_AUD_12288 		32
+#define JH7100_CLK_AUD_END 		33
+
 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */

include/dt-bindings/reset/starfive-jh7100.h

@@ -123,4 +123,27 @@
 
 #define JH7100_RSTN_END			114
 
+/*  audio resets  */
+#define JH7100_AUDRSTN_APB_BUS		0
+#define JH7100_AUDRSTN_APB_I2SADC	1
+#define JH7100_AUDRSTN_I2SADC_SRST	2
+#define JH7100_AUDRSTN_APB_PDM		3
+#define JH7100_AUDRSTN_APB_I2SVAD	4
+#define JH7100_AUDRSTN_I2SVAD_SRST	5
+#define JH7100_AUDRSTN_APB_SPDIF	6
+#define JH7100_AUDRSTN_APB_PWMDAC	7
+#define JH7100_AUDRSTN_APB_I2SDAC	8
+#define JH7100_AUDRSTN_I2SDAC_SRST	9
+#define JH7100_AUDRSTN_APB_I2S1 	10
+#define JH7100_AUDRSTN_I2S1_SRST 	11
+#define JH7100_AUDRSTN_APB_I2SDAC16K 	12
+#define JH7100_AUDRSTN_I2SDAC16K_SRST 	13
+#define JH7100_AUDRSTN_DMA1P_AHB 	14
+#define JH7100_AUDRSTN_APB_USB 		15
+#define JH7100_AUDRSTN_AXI_USB		16
+#define JH7100_AUDRSTN_USB_PWRUP	17
+#define JH7100_AUDRSTN_USB_PONRST	18
+
+#define JH7100_AUDIO_RSTN_END		19
+
 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */