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hal-fenghal-feng
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riscv: dts: starfive: Add full support for JH7110 and VisionFive 2 board
Merge all StarFive dts patches together. Signed-off-by: Hal Feng <[email protected]>
1 parent cb79f61 commit fbd9d8b

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4 files changed

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‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,16 @@
1111
model = "StarFive VisionFive 2 v1.2A";
1212
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
1313
};
14+
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&gmac1 {
16+
phy-mode = "rmii";
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assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
18+
<&syscrg JH7110_SYSCLK_GMAC1_RX>;
19+
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
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<&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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};
22+
23+
&phy0 {
24+
rx-internal-delay-ps = <1900>;
25+
tx-internal-delay-ps = <1350>;
26+
};

‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,30 @@
1111
model = "StarFive VisionFive 2 v1.3B";
1212
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
1313
};
14+
15+
&gmac0 {
16+
starfive,tx-use-rgmii-clk;
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assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18+
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
19+
};
20+
21+
&gmac1 {
22+
starfive,tx-use-rgmii-clk;
23+
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
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assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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};
26+
27+
&phy0 {
28+
motorcomm,tx-clk-adj-enabled;
29+
motorcomm,tx-clk-100-inverted;
30+
motorcomm,tx-clk-1000-inverted;
31+
rx-internal-delay-ps = <1900>;
32+
tx-internal-delay-ps = <1500>;
33+
};
34+
35+
&phy1 {
36+
motorcomm,tx-clk-adj-enabled;
37+
motorcomm,tx-clk-100-inverted;
38+
rx-internal-delay-ps = <0>;
39+
tx-internal-delay-ps = <0>;
40+
};

‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi‎

Lines changed: 178 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111

1212
/ {
1313
aliases {
14+
ethernet0 = &gmac0;
15+
ethernet1 = &gmac1;
1416
i2c0 = &i2c0;
1517
i2c2 = &i2c2;
1618
i2c5 = &i2c5;
@@ -31,13 +33,45 @@
3133
reg = <0x0 0x40000000 0x1 0x0>;
3234
};
3335

36+
thermal-zones {
37+
cpu-thermal {
38+
polling-delay-passive = <250>;
39+
polling-delay = <15000>;
40+
41+
thermal-sensors = <&sfctemp>;
42+
43+
cooling-maps {
44+
};
45+
46+
trips {
47+
cpu_alert0: cpu_alert0 {
48+
/* milliCelsius */
49+
temperature = <75000>;
50+
hysteresis = <2000>;
51+
type = "passive";
52+
};
53+
54+
cpu_crit: cpu_crit {
55+
/* milliCelsius */
56+
temperature = <90000>;
57+
hysteresis = <2000>;
58+
type = "critical";
59+
};
60+
};
61+
};
62+
};
63+
3464
gpio-restart {
3565
compatible = "gpio-restart";
3666
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
3767
priority = <224>;
3868
};
3969
};
4070

71+
&dvp_clk {
72+
clock-frequency = <74250000>;
73+
};
74+
4175
&gmac0_rgmii_rxin {
4276
clock-frequency = <125000000>;
4377
};
@@ -54,6 +88,10 @@
5488
clock-frequency = <50000000>;
5589
};
5690

91+
&hdmitx0_pixelclk {
92+
clock-frequency = <297000000>;
93+
};
94+
5795
&i2srx_bclk_ext {
5896
clock-frequency = <12288000>;
5997
};
@@ -86,6 +124,38 @@
86124
clock-frequency = <49152000>;
87125
};
88126

127+
&gmac0 {
128+
phy-handle = <&phy0>;
129+
phy-mode = "rgmii-id";
130+
status = "okay";
131+
132+
mdio {
133+
#address-cells = <1>;
134+
#size-cells = <0>;
135+
compatible = "snps,dwmac-mdio";
136+
137+
phy0: ethernet-phy@0 {
138+
reg = <0>;
139+
};
140+
};
141+
};
142+
143+
&gmac1 {
144+
phy-handle = <&phy1>;
145+
phy-mode = "rgmii-id";
146+
status = "okay";
147+
148+
mdio {
149+
#address-cells = <1>;
150+
#size-cells = <0>;
151+
compatible = "snps,dwmac-mdio";
152+
153+
phy1: ethernet-phy@1 {
154+
reg = <0>;
155+
};
156+
};
157+
};
158+
89159
&i2c0 {
90160
clock-frequency = <100000>;
91161
i2c-sda-hold-time-ns = <300>;
@@ -126,6 +196,49 @@
126196
status = "okay";
127197
};
128198

199+
&mmc0 {
200+
max-frequency = <100000000>;
201+
bus-width = <8>;
202+
cap-mmc-highspeed;
203+
mmc-ddr-1_8v;
204+
mmc-hs200-1_8v;
205+
non-removable;
206+
cap-mmc-hw-reset;
207+
post-power-on-delay-ms = <200>;
208+
status = "okay";
209+
};
210+
211+
&mmc1 {
212+
max-frequency = <100000000>;
213+
bus-width = <4>;
214+
no-sdio;
215+
no-mmc;
216+
broken-cd;
217+
cap-sd-highspeed;
218+
post-power-on-delay-ms = <200>;
219+
status = "okay";
220+
};
221+
222+
&pcie0 {
223+
pinctrl-names = "default";
224+
reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
225+
phys = <&pciephy0>;
226+
status = "okay";
227+
};
228+
229+
&pcie1 {
230+
pinctrl-names = "default";
231+
reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
232+
phys = <&pciephy1>;
233+
status = "okay";
234+
};
235+
236+
&ptc {
237+
pinctrl-names = "default";
238+
pinctrl-0 = <&pwm_pins>;
239+
status = "okay";
240+
};
241+
129242
&sysgpio {
130243
i2c0_pins: i2c0-0 {
131244
i2c-pins {
@@ -183,6 +296,64 @@
183296
};
184297
};
185298

299+
pcie0_wake_default: pcie0_wake_default {
300+
wake-pins {
301+
pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
302+
bias-disable;
303+
drive-strength = <2>;
304+
input-enable;
305+
input-schmitt-disable;
306+
slew-rate = <0>;
307+
};
308+
};
309+
310+
pcie0_clkreq_default: pcie0_clkreq_default {
311+
clkreq-pins {
312+
bias-disable;
313+
pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
314+
drive-strength = <2>;
315+
input-enable;
316+
input-schmitt-disable;
317+
slew-rate = <0>;
318+
};
319+
};
320+
321+
pcie1_wake_default: pcie1_wake_default {
322+
wake-pins {
323+
bias-disable;
324+
pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
325+
drive-strength = <2>;
326+
input-enable;
327+
input-schmitt-disable;
328+
slew-rate = <0>;
329+
};
330+
};
331+
332+
pcie1_clkreq_default: pcie1_clkreq_default {
333+
clkreq-pins {
334+
bias-disable;
335+
pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
336+
drive-strength = <2>;
337+
input-enable;
338+
input-schmitt-disable;
339+
slew-rate = <0>;
340+
};
341+
};
342+
343+
pwm_pins: pwm-0 {
344+
pwm-pins {
345+
pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
346+
GPOEN_SYS_PWM0_CHANNEL0, GPI_NONE)>,
347+
<GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
348+
GPOEN_SYS_PWM0_CHANNEL1, GPI_NONE)>;
349+
bias-disable;
350+
drive-strength = <12>;
351+
input-disable;
352+
input-schmitt-disable;
353+
slew-rate = <0>;
354+
};
355+
};
356+
186357
uart0_pins: uart0-0 {
187358
tx-pins {
188359
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
@@ -213,3 +384,10 @@
213384
pinctrl-0 = <&uart0_pins>;
214385
status = "okay";
215386
};
387+
388+
&usb0 {
389+
status = "okay";
390+
usbdrd_cdns3: usb@0 {
391+
dr_mode = "peripheral";
392+
};
393+
};

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