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[L4] Update STM32L4xx CMSIS to v1.6.0
Included in STM32CubeL4 FW V1.15.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 8b42748 commit f99f797

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55 files changed

+46687
-789
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h

Lines changed: 287 additions & 288 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h

Lines changed: 287 additions & 288 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -917,7 +917,9 @@ typedef struct
917917
* @{
918918
*/
919919
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
920-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
920+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
921+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
922+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
921923
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
922924
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
923925
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -933,6 +935,11 @@ typedef struct
933935
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
934936
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
935937

938+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
939+
940+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
941+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
942+
936943
/*!< Peripheral memory map */
937944
#define APB1PERIPH_BASE PERIPH_BASE
938945
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -10236,8 +10243,12 @@ typedef struct
1023610243
#define RTC_TAMPER1_SUPPORT
1023710244
#define RTC_TAMPER2_SUPPORT
1023810245
#define RTC_TAMPER3_SUPPORT
10246+
1023910247
#define RTC_WAKEUP_SUPPORT
1024010248
#define RTC_BACKUP_SUPPORT
10249+
/******************** Number of backup registers ******************************/
10250+
#define RTC_BKP_NUMBER 32U
10251+
1024110252

1024210253
/******************** Bits definition for RTC_TR register *******************/
1024310254
#define RTC_TR_PM_Pos (22U)
@@ -10994,9 +11005,6 @@ typedef struct
1099411005
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1099511006
#define RTC_BKP31R RTC_BKP31R_Msk
1099611007

10997-
/******************** Number of backup registers ******************************/
10998-
#define RTC_BKP_NUMBER 32U
10999-
1100011008
/******************************************************************************/
1100111009
/* */
1100211010
/* Serial Audio Interface */
@@ -14933,9 +14941,6 @@ typedef struct
1493314941
((INSTANCE) == TIM15) || \
1493414942
((INSTANCE) == TIM16))
1493514943

14936-
/****************** TIM Instances : supporting synchronization ****************/
14937-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
14938-
1493914944
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1494014945
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1494114946

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -913,7 +913,9 @@ typedef struct
913913
* @{
914914
*/
915915
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
916-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
916+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
917+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
918+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
917919
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
918920
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
919921
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -929,6 +931,11 @@ typedef struct
929931
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
930932
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
931933

934+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
935+
936+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
937+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
938+
932939
/*!< Peripheral memory map */
933940
#define APB1PERIPH_BASE PERIPH_BASE
934941
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -9838,8 +9845,12 @@ typedef struct
98389845
* @brief Specific device feature definitions
98399846
*/
98409847
#define RTC_TAMPER2_SUPPORT
9848+
98419849
#define RTC_WAKEUP_SUPPORT
98429850
#define RTC_BACKUP_SUPPORT
9851+
/******************** Number of backup registers ******************************/
9852+
#define RTC_BKP_NUMBER 32U
9853+
98439854

98449855
/******************** Bits definition for RTC_TR register *******************/
98459856
#define RTC_TR_PM_Pos (22U)
@@ -10560,9 +10571,6 @@ typedef struct
1056010571
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1056110572
#define RTC_BKP31R RTC_BKP31R_Msk
1056210573

10563-
/******************** Number of backup registers ******************************/
10564-
#define RTC_BKP_NUMBER 32U
10565-
1056610574
/******************************************************************************/
1056710575
/* */
1056810576
/* Serial Audio Interface */
@@ -14732,9 +14740,6 @@ typedef struct
1473214740
((INSTANCE) == TIM15) || \
1473314741
((INSTANCE) == TIM16))
1473414742

14735-
/****************** TIM Instances : supporting synchronization ****************/
14736-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
14737-
1473814743
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1473914744
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1474014745

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -971,7 +971,9 @@ typedef struct
971971
* @{
972972
*/
973973
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
974-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
974+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
975+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
976+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
975977
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
976978
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
977979
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -987,6 +989,11 @@ typedef struct
987989
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
988990
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
989991

992+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
993+
994+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
995+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
996+
990997
/*!< Peripheral memory map */
991998
#define APB1PERIPH_BASE PERIPH_BASE
992999
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -10346,8 +10353,12 @@ typedef struct
1034610353
#define RTC_TAMPER1_SUPPORT
1034710354
#define RTC_TAMPER2_SUPPORT
1034810355
#define RTC_TAMPER3_SUPPORT
10356+
1034910357
#define RTC_WAKEUP_SUPPORT
1035010358
#define RTC_BACKUP_SUPPORT
10359+
/******************** Number of backup registers ******************************/
10360+
#define RTC_BKP_NUMBER 32U
10361+
1035110362

1035210363
/******************** Bits definition for RTC_TR register *******************/
1035310364
#define RTC_TR_PM_Pos (22U)
@@ -11104,9 +11115,6 @@ typedef struct
1110411115
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1110511116
#define RTC_BKP31R RTC_BKP31R_Msk
1110611117

11107-
/******************** Number of backup registers ******************************/
11108-
#define RTC_BKP_NUMBER 32U
11109-
1111011118
/******************************************************************************/
1111111119
/* */
1111211120
/* Serial Audio Interface */
@@ -15826,9 +15834,6 @@ typedef struct
1582615834
((INSTANCE) == TIM15) || \
1582715835
((INSTANCE) == TIM16))
1582815836

15829-
/****************** TIM Instances : supporting synchronization ****************/
15830-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
15831-
1583215837
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1583315838
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1583415839

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -946,7 +946,9 @@ typedef struct
946946
* @{
947947
*/
948948
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
949-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
949+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
950+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
951+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
950952
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
951953
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
952954
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -962,6 +964,11 @@ typedef struct
962964
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
963965
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
964966

967+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
968+
969+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
970+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
971+
965972
/*!< Peripheral memory map */
966973
#define APB1PERIPH_BASE PERIPH_BASE
967974
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -10063,8 +10070,12 @@ typedef struct
1006310070
* @brief Specific device feature definitions
1006410071
*/
1006510072
#define RTC_TAMPER2_SUPPORT
10073+
1006610074
#define RTC_WAKEUP_SUPPORT
1006710075
#define RTC_BACKUP_SUPPORT
10076+
/******************** Number of backup registers ******************************/
10077+
#define RTC_BKP_NUMBER 32U
10078+
1006810079

1006910080
/******************** Bits definition for RTC_TR register *******************/
1007010081
#define RTC_TR_PM_Pos (22U)
@@ -10785,9 +10796,6 @@ typedef struct
1078510796
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1078610797
#define RTC_BKP31R RTC_BKP31R_Msk
1078710798

10788-
/******************** Number of backup registers ******************************/
10789-
#define RTC_BKP_NUMBER 32U
10790-
1079110799
/******************************************************************************/
1079210800
/* */
1079310801
/* Serial Audio Interface */
@@ -14960,9 +14968,6 @@ typedef struct
1496014968
((INSTANCE) == TIM15) || \
1496114969
((INSTANCE) == TIM16))
1496214970

14963-
/****************** TIM Instances : supporting synchronization ****************/
14964-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
14965-
1496614971
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1496714972
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1496814973

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1004,7 +1004,9 @@ typedef struct
10041004
* @{
10051005
*/
10061006
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
1007-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
1007+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
1008+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
1009+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
10081010
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
10091011
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
10101012
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -1020,6 +1022,11 @@ typedef struct
10201022
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
10211023
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
10221024

1025+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
1026+
1027+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
1028+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
1029+
10231030
/*!< Peripheral memory map */
10241031
#define APB1PERIPH_BASE PERIPH_BASE
10251032
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -10571,8 +10578,12 @@ typedef struct
1057110578
#define RTC_TAMPER1_SUPPORT
1057210579
#define RTC_TAMPER2_SUPPORT
1057310580
#define RTC_TAMPER3_SUPPORT
10581+
1057410582
#define RTC_WAKEUP_SUPPORT
1057510583
#define RTC_BACKUP_SUPPORT
10584+
/******************** Number of backup registers ******************************/
10585+
#define RTC_BKP_NUMBER 32U
10586+
1057610587

1057710588
/******************** Bits definition for RTC_TR register *******************/
1057810589
#define RTC_TR_PM_Pos (22U)
@@ -11329,9 +11340,6 @@ typedef struct
1132911340
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1133011341
#define RTC_BKP31R RTC_BKP31R_Msk
1133111342

11332-
/******************** Number of backup registers ******************************/
11333-
#define RTC_BKP_NUMBER 32U
11334-
1133511343
/******************************************************************************/
1133611344
/* */
1133711345
/* Serial Audio Interface */
@@ -16054,9 +16062,6 @@ typedef struct
1605416062
((INSTANCE) == TIM15) || \
1605516063
((INSTANCE) == TIM16))
1605616064

16057-
/****************** TIM Instances : supporting synchronization ****************/
16058-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
16059-
1606016065
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1606116066
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1606216067

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -937,6 +937,8 @@ typedef struct
937937
* @{
938938
*/
939939
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 512 KB) base address */
940+
#define FLASH_END (0x0807FFFFUL) /*!< FLASH END address */
941+
#define FLASH_BANK1_END (0x0807FFFFUL) /*!< FLASH END address of bank1 */
940942
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 128 KB) base address */
941943
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */
942944
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
@@ -953,6 +955,11 @@ typedef struct
953955
#define SRAM1_SIZE_MAX (0x00020000UL) /*!< maximum SRAM1 size (up to 128 KBytes) */
954956
#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */
955957

958+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
959+
960+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \
961+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
962+
956963
/*!< Peripheral memory map */
957964
#define APB1PERIPH_BASE PERIPH_BASE
958965
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -10520,8 +10527,12 @@ typedef struct
1052010527
#define RTC_TAMPER1_SUPPORT
1052110528
#define RTC_TAMPER2_SUPPORT
1052210529
#define RTC_TAMPER3_SUPPORT
10530+
1052310531
#define RTC_WAKEUP_SUPPORT
1052410532
#define RTC_BACKUP_SUPPORT
10533+
/******************** Number of backup registers ******************************/
10534+
#define RTC_BKP_NUMBER 32U
10535+
1052510536

1052610537
/******************** Bits definition for RTC_TR register *******************/
1052710538
#define RTC_TR_PM_Pos (22U)
@@ -11278,9 +11289,6 @@ typedef struct
1127811289
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1127911290
#define RTC_BKP31R RTC_BKP31R_Msk
1128011291

11281-
/******************** Number of backup registers ******************************/
11282-
#define RTC_BKP_NUMBER 32U
11283-
1128411292
/******************************************************************************/
1128511293
/* */
1128611294
/* Serial Audio Interface */
@@ -15181,9 +15189,6 @@ typedef struct
1518115189
((INSTANCE) == TIM15) || \
1518215190
((INSTANCE) == TIM16))
1518315191

15184-
/****************** TIM Instances : supporting synchronization ****************/
15185-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
15186-
1518715192
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1518815193
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1518915194

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -976,6 +976,8 @@ typedef struct
976976
* @{
977977
*/
978978
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 512 KB) base address */
979+
#define FLASH_END (0x0807FFFFUL) /*!< FLASH END address */
980+
#define FLASH_BANK1_END (0x0807FFFFUL) /*!< FLASH END address of bank1 */
979981
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 128 KB) base address */
980982
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */
981983
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
@@ -992,6 +994,11 @@ typedef struct
992994
#define SRAM1_SIZE_MAX (0x00020000UL) /*!< maximum SRAM1 size (up to 128 KBytes) */
993995
#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */
994996

997+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
998+
999+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \
1000+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
1001+
9951002
/*!< Peripheral memory map */
9961003
#define APB1PERIPH_BASE PERIPH_BASE
9971004
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -10598,8 +10605,12 @@ typedef struct
1059810605
#define RTC_TAMPER1_SUPPORT
1059910606
#define RTC_TAMPER2_SUPPORT
1060010607
#define RTC_TAMPER3_SUPPORT
10608+
1060110609
#define RTC_WAKEUP_SUPPORT
1060210610
#define RTC_BACKUP_SUPPORT
10611+
/******************** Number of backup registers ******************************/
10612+
#define RTC_BKP_NUMBER 32U
10613+
1060310614

1060410615
/******************** Bits definition for RTC_TR register *******************/
1060510616
#define RTC_TR_PM_Pos (22U)
@@ -11356,9 +11367,6 @@ typedef struct
1135611367
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1135711368
#define RTC_BKP31R RTC_BKP31R_Msk
1135811369

11359-
/******************** Number of backup registers ******************************/
11360-
#define RTC_BKP_NUMBER 32U
11361-
1136211370
/******************************************************************************/
1136311371
/* */
1136411372
/* Serial Audio Interface */
@@ -15920,9 +15928,6 @@ typedef struct
1592015928
((INSTANCE) == TIM15) || \
1592115929
((INSTANCE) == TIM16))
1592215930

15923-
/****************** TIM Instances : supporting synchronization ****************/
15924-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
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/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
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#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
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