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astprov conversion for result types
1 parent 5f77e9d commit 03751ba

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7 files changed

+77
-29
lines changed

7 files changed

+77
-29
lines changed

chb/app/CHVersion.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
chbversion: str = "0.3.0-20250210"
1+
chbversion: str = "0.3.0-20250308"

chb/arm/ARMCallOpcode.py

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -240,7 +240,12 @@ def ast_call_prov(
240240
ctinfo = finfo.call_target_info(iaddr)
241241
ftype = ctinfo.target_interface.bctype
242242
if ftype is not None:
243-
astfntype = ftype.convert(astree.typconverter)
243+
try:
244+
astfntype = ftype.convert(astree.typconverter)
245+
except UF.CHBError as e:
246+
chklogger.logger.warning(
247+
"Type conversion of function type was unsuccessful: %s",
248+
str(e))
244249

245250
if xdata.is_bx_call:
246251
# indirect call

chb/arm/opcodes/ARMBranch.py

Lines changed: 27 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -90,14 +90,29 @@ def xtgt(self) -> "XXpr":
9090
index = 1 if self.is_unconditional else 4
9191
return self.xpr(index, "xtgt")
9292

93+
@property
94+
def is_xtgt_known(self) -> bool:
95+
index = 1 if self.is_unconditional else 4
96+
return self.xdata.xprs_r[index] is not None
97+
9398
@property
9499
def annotation(self) -> str:
95-
if self._xdata.has_branch_conditions():
96-
return "if " + str(self.tcond) + " then goto " + str(self.xtgt)
97-
elif self.is_unconditional:
98-
return "goto " + str(self.xtgt)
100+
if self.is_ok:
101+
if self._xdata.has_branch_conditions():
102+
return "if " + str(self.tcond) + " then goto " + str(self.xtgt)
103+
elif self.is_unconditional:
104+
return "goto " + str(self.xtgt)
105+
else:
106+
return "?"
107+
elif self.is_xtgt_known:
108+
if self._xdata.has_branch_conditions():
109+
return "if " + str(self.txpr) + " then goto " + str(self.xtgt)
110+
elif self.is_unconditional:
111+
return "goto " + str(self.xtgt)
112+
else:
113+
return "?"
99114
else:
100-
return "?"
115+
return "Error value"
101116

102117

103118
@armregistry.register_tag("B", ARMOpcode)
@@ -151,7 +166,10 @@ def ft_conditions_basic(self, xdata: InstrXData) -> Sequence[XXpr]:
151166
def ft_conditions(self, xdata: InstrXData) -> Sequence[XXpr]:
152167
xd = ARMBranchXData(xdata)
153168
if xdata.has_branch_conditions():
154-
return [xd.fcond, xd.tcond]
169+
if xd.is_ok:
170+
return [xd.fcond, xd.tcond]
171+
else:
172+
return [xd.fxpr, xd.txpr]
155173
else:
156174
return []
157175

@@ -191,7 +209,7 @@ def annotation(self, xdata: InstrXData) -> str:
191209
else:
192210
return xd.annotation
193211
else:
194-
return "Error value"
212+
return xd.annotation
195213

196214
def target_expr_ast(
197215
self,
@@ -264,6 +282,8 @@ def default(condition: XXpr) -> AST.ASTExpr:
264282
# case there are no rewritten variables, but this still has to be
265283
# validated with more instances.
266284

285+
xd = ARMBranchXData(xdata)
286+
267287
ftconds_basic = self.ft_conditions(xdata)
268288
ftconds = self.ft_conditions(xdata)
269289

chb/arm/opcodes/ARMCompare.py

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,8 @@ def result(self) -> "XXpr":
7878
@property
7979
def annotation(self) -> str:
8080
ann = "compare " + str(self.xrn) + " and " + str(self.xrm)
81-
ann += " (" + str(self.result) + ")"
81+
if self.is_ok:
82+
ann += " (" + str(self.result) + ")"
8283
return self.add_instruction_condition(ann)
8384

8485

@@ -118,10 +119,7 @@ def opargs(self) -> List[ARMOperand]:
118119

119120
def annotation(self, xdata: InstrXData) -> str:
120121
xd = ARMCompareXData(xdata)
121-
if xd.is_ok:
122-
return xd.annotation
123-
else:
124-
return "Error value"
122+
return xd.annotation
125123

126124
def ast_prov(
127125
self,
@@ -149,16 +147,17 @@ def ast_prov(
149147

150148
# high-level assignment
151149

152-
xd = ARMCompareXData(xdata)
153-
if not xd.is_ok:
154-
chklogger.logger.error(
155-
"Error value encountered at address %s", iaddr)
156-
return ([], [])
157-
158-
rhs = xd.result
159150
rdefs = xdata.reachingdefs
160-
161-
hl_rhs = XU.xxpr_to_ast_def_expr(rhs, xdata, iaddr, astree)
151+
xd = ARMCompareXData(xdata)
152+
if xd.is_ok:
153+
rhs = xd.result
154+
hl_rhs = XU.xxpr_to_ast_def_expr(rhs, xdata, iaddr, astree)
155+
else:
156+
rhs1 = xd.xrn
157+
rhs2 = xd.xrm
158+
hl_rhs1 = XU.xxpr_to_ast_def_expr(rhs1, xdata, iaddr, astree)
159+
hl_rhs2 = XU.xxpr_to_ast_def_expr(rhs2, xdata, iaddr, astree)
160+
hl_rhs = astree.mk_binary_op("minus", hl_rhs1, hl_rhs2)
162161

163162
hl_assign = astree.mk_assign(
164163
astree.ignoredlhs,

chb/arm/opcodes/ARMStoreMultipleIncrementAfter.py

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,26 @@ def copysize(self) -> int:
104104
else:
105105
raise UF.CHBError("Not an ldmstm aggregate")
106106

107+
@property
108+
def regcount(self) -> int:
109+
return len(self.xdata.vars_r) - 1
110+
111+
@property
112+
def baselhs(self) -> "XVariable":
113+
return self.var(0, "baselhs")
114+
115+
@property
116+
def is_baselhs_known(self) -> bool:
117+
return self.xdata.vars_r[0] is not None
118+
119+
@property
120+
def memlhss(self) -> List["XVariable"]:
121+
return [self.var(i, "memlhs-" + str(i)) for i in range(1, self.regcount + 1)]
122+
123+
@property
124+
def rhss(self) -> List["XXpr"]:
125+
return [self.xpr(i, "rhs-" + str(i)) for i in range(3, self.regcount + 3)]
126+
107127
@property
108128
def annotation(self) -> str:
109129
if self.is_ok:
@@ -117,7 +137,10 @@ def annotation(self) -> str:
117137
+ str(self.copysize)
118138
+ ")")
119139
else:
120-
return "not yet supported"
140+
assigns = []
141+
for (memlhs, rhs) in zip(self.memlhss, self.rhss):
142+
assigns.append(str(memlhs) + " := " + str(rhs))
143+
return "; ".join(assigns)
121144
else:
122145
if self.is_ldmstm_aggregate:
123146
if self.is_xxdst_unknown and self.is_xxsrc_unknown:

chb/arm/opcodes/ARMStoreRegisterHalfword.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ def annotation(self) -> str:
9797
if self.is_ok:
9898
assignment = str(self.vmem) + " := " + str(self.xxrt)
9999
elif not self.is_xxrt_known:
100-
assignment = "(*" + str(self.xaddr) + ") := Error value"
100+
assignment = "(*" + str(self.xaddr) + ") := " + str(self.xrt)
101101
elif self.is_vmem_unknown and self.is_address_known:
102102
assignment = "*(" + str(self.xaddr) + ") := " + str(self.xxrt)
103103
else:

chb/invariants/XXprUtil.py

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -659,10 +659,11 @@ def vargument_deref_value_to_ast_lval_expression(
659659
elif tgttype.is_scalar and coff == 0:
660660
return astree.mk_memref_expr(xinitarg, anonymous=anonymous)
661661

662-
chklogger.logger.error(
663-
"AST conversion of argument deref value: %s with offset %s and type %s "
664-
+ "not yet handled at %s",
665-
str(basevar), str(offset), str(argtype), iaddr)
662+
if not anonymous:
663+
chklogger.logger.error(
664+
"AST conversion of argument deref value: %s with offset %s and type %s "
665+
+ "not yet handled at %s",
666+
str(basevar), str(offset), str(argtype), iaddr)
666667

667668
return astree.mk_temp_lval_expression()
668669

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