ARM:LDM: update for conversion to C expressions

Author: sipma

chb/arm/opcodes/ARMLoadMultipleIncrementAfter.py

@@ -25,7 +25,7 @@
 # SOFTWARE.
 # ------------------------------------------------------------------------------
 
-from typing import List, Tuple, TYPE_CHECKING
+from typing import Iterable, List, Tuple, TYPE_CHECKING
 
 from chb.app.InstrXData import InstrXData
 
@@ -49,6 +49,20 @@
 
 
 class ARMLoadMultipleIncrementAfterXData(ARMOpcodeXData):
+    """Data format:
+    - variables:
+    0: baselhs
+    1..n: lhsvars
+
+    - expressions:
+    0: baserhs
+    1..n: memrhss
+    n+1..2n: rmemrhss (memrhss, rewritten)
+    2n+1..3n: xaddrs
+
+    - c expressions:
+    0..n-1: cmemrhss
+    """
 
     def __init__(self, xdata: InstrXData) -> None:
         ARMOpcodeXData.__init__(self, xdata)
@@ -57,6 +71,23 @@ def __init__(self, xdata: InstrXData) -> None:
     def regcount(self) -> int:
         return len(self.xdata.vars_r) - 1
 
+    def has_index(self, index: int) -> bool:
+        """returns true if index is between 1 and regcount (inclusive)."""
+
+        return index > 0 and index <= self.regcount
+
+    @property
+    def memrhs_range(self) -> Iterable[int]:
+        return range(1, self.regcount + 1)
+
+    @property
+    def rmemrhs_range(self) -> Iterable[int]:
+        return range(self.regcount + 1, (2 * self.regcount) + 1)
+
+    @property
+    def xaddr_range(self) -> Iterable[int]:
+        return range((2 * self.regcount) + 1, (3 * self.regcount) + 1)
+
     @property
     def baselhs(self) -> "XVariable":
         return self.var(0, "baselhs")
@@ -65,23 +96,106 @@ def baselhs(self) -> "XVariable":
     def lhsvars(self) -> List["XVariable"]:
         return [self.var(i, "lhsvar") for i in range(1, self.regcount + 1)]
 
+    def lhsvar(self, index: int) -> "XVariable":
+        """returns the lhsvar at (1-based) position index"""
+
+        if self.has_index(index):
+            return self.lhsvars[index]
+        else:
+            raise UF.CHBError("LDM: index out of bounds: " + str(index))
+
     @property
     def baserhs(self) -> "XXpr":
         return self.xpr(0, "baserhs")
 
     @property
-    def rhsexprs(self) -> List["XXpr"]:
-        return [self.xpr(i, "rhsexpr") for i in range(1, self.regcount + 1)]
+    def memrhss(self) -> List["XXpr"]:
+        return [self.xpr(i, "memrhs") for i in self.memrhs_range]
+
+    @property
+    def are_memrhss_ok(self) -> bool:
+        return all(self.is_xpr_ok(i) for i in self.memrhs_range)
+
+    def memrhs(self, index) -> "XXpr":
+        """returns the rhs expression at (1-based) position index"""
+
+        if self.has_index(index):
+            if self.are_memrhss_ok:
+                return self.memrhss[index - 1]
+            else:
+                raise UF.CHBError("LDM: memrhss have error values")
+        else:
+            raise UF.CHBError("LDM: index out of bounds for memrhs")
+
+    @property
+    def rmemrhss(self) -> List["XXpr"]:
+        return [self.xpr(i, "rmemrhs") for i in self.rmemrhs_range]
+
+    @property
+    def are_rmemrhss_ok(self) -> bool:
+        return all(self.is_xpr_ok(i) for i in self.rmemrhs_range)
+
+    def rmemrhs(self, index) -> "XXpr":
+        """returns the rewritten rhs expr at (1-based) position index"""
+
+        if self.has_index(index):
+            if self.are_rmemrhss_ok:
+                return self.rmemrhss[index - 1]
+            else:
+                raise UF.CHBError("LDM: rmemrhss have error values")
+        else:
+            raise UF.CHBError("LDM: index out of bounds for rmemrhs")
 
     @property
     def xaddrs(self) -> List["XXpr"]:
-        return [self.xpr(i, "xaddr")
-                for i in range(self.regcount + 1, (2 * self.regcount) + 3)]
+        return [self.xpr(i, "xaddr") for i in self.xaddr_range]
+
+    @property
+    def are_xaddrs_ok(self) -> bool:
+        return all(self.is_xpr_ok(i) for i in self.xaddr_range)
+
+    def xaddr(self, index) -> "XXpr":
+        """returns the rhs addr at (1-based) position index"""
+
+        if self.has_index(index):
+            if self.are_xaddrs_ok:
+                return self.xaddrs[index - 1]
+            else:
+                raise UF.CHBError("LDM: xaddrs have error values")
+        else:
+            raise UF.CHBError("LDM: index out of bounds for xaddr")
+
+    @property
+    def cmemrhss(self) -> List["XXpr"]:
+        return [self.cxpr(i, "cmemrhs") for i in range(0, self.regcount)]
+
+    @property
+    def are_cmemrhss_ok(self) -> bool:
+        return all(self.is_cxpr_ok(i) for i in range(0, self.regcount))
+
+    def cmemrhs(self, index) -> "XXpr":
+        """returns the rhs addr at (1-based) position index"""
+
+        if self.has_index(index):
+            if self.are_cmemrhss_ok:
+                return self.cmemrhss[index - 1]
+            else:
+                raise UF.CHBError("LDM: cmemrhss have error values")
+        else:
+            raise UF.CHBError("LDM: index out of bounds cmemrhs")
 
     @property
     def annotation(self) -> str:
-        pairs = zip(self.lhsvars, self.rhsexprs)
-        assigns = "; ".join(str(v) + " := " + str(x) for (x, v) in pairs)
+        if self.are_rmemrhss_ok:
+            pairs = list(zip(self.lhsvars, self.rmemrhss))
+        elif self.are_memrhss_ok:
+            pairs = list(zip(self.lhsvars, self.memrhss))
+        else:
+            pairs = []
+        if len(pairs) > 0:
+            assigns = "; ".join(str(v) + " := " + str(x) for (x, v) in pairs)
+        else:
+            assigns = "unknown rhs memory"
         wbu = self.writeback_update()
         return self.add_instruction_condition(assigns + wbu)
 
@@ -98,14 +212,8 @@ class ARMLoadMultipleIncrementAfter(ARMOpcode):
     args[2]: index of registers in arm dictionary
     args[3]: index of base memory address
 
-    xdata format: vv[n]xxxx[n]rr[n]dd[n]hh[n]
-    ----------------------------------------
-    vars[0]: base lhs
-    vars[1..n]: register lhss
-    xprs[0]: base rhs
-    xprs[1]: updated base (may be unchanged in case of no writeback)
-    xprs[2]: updated base (simplified)
-    xprs[3..n+2]: values of memory locations read
+    xdata format:
+    -------------
     rdefs[0]: reaching definition base register
     rdefs[1..n]: reaching definition memory locations
     uses[0]: base lhs
@@ -143,10 +251,7 @@ def is_load_instruction(self, xdata: InstrXData) -> bool:
 
     def annotation(self, xdata: InstrXData) -> str:
         xd = ARMLoadMultipleIncrementAfterXData(xdata)
-        if xd.is_ok:
-            return xd.annotation
-        else:
-            return "Error value"
+        return xd.annotation
 
     # -------------------------------------------------------------------------
     # address = R[n];
@@ -168,15 +273,22 @@ def ast_prov(
                 List[AST.ASTInstruction], List[AST.ASTInstruction]]:
 
         xd = ARMLoadMultipleIncrementAfterXData(xdata)
-        if not xd.is_ok:
+
+        if xd.are_cmemrhss_ok:
+            rhsexprs = xd.cmemrhss
+        elif xd.are_rmemrhss_ok:
+            rhsexprs = xd.rmemrhss
+        elif xd.are_memrhss_ok:
+            rhsexprs = xd.memrhss
+
+        else:
             chklogger.logger.error(
-                "Error value encountered at address %s", iaddr)
+                "LDM: Error value encountered at address %s", iaddr)
             return ([], [])
 
         baselhs = xd.baselhs
         lhsvars = xd.lhsvars
         baserhs = xd.baserhs
-        rhsexprs = xd.rhsexprs
 
         baserdef = xdata.reachingdefs[0]
         memrdefs = xdata.reachingdefs[1:]