ARM:LDR: restructure writeback

Author: sipma

chb/app/InstrXData.py

@@ -549,6 +549,17 @@ def get_base_update_xpr(self) -> XXpr:
                 "Unexpected error value in base-update expression")
         return self.xprdictionary.xpr(xbuval)
 
+    def get_base_update_cxpr(self) -> XXpr:
+        cbutag = next(t for t in self.tags if t.startswith("cbu:"))
+        cix = int(cbutag[4:])
+        cbuval = self.args[cix]
+        if cbuval == -2:
+            chklogger.logger.info(
+                "Base update c expression unavailable, fall back to expression")
+            return self.get_base_update_xpr()
+        else:
+            return self.xprdictionary.xpr(cbuval)
+
     def has_return_xpr(self) -> bool:
         return any(s.startswith("return:") for s in self.tags)
 

chb/arm/ARMOpcode.py

@@ -213,11 +213,18 @@ def get_base_update_xpr(self) -> "XXpr":
             raise UF.CHBError(
                 self.__class__.__name__ + " does not have writeback")
 
+    def get_base_update_cxpr(self) -> "XXpr":
+        if self.is_writeback:
+            return self.xdata.get_base_update_cxpr()
+        else:
+            raise UF.CHBError(
+                self.__class__.__name__ + " does not have writeback")
+
     def writeback_update(self) -> str:
         if self.xdata.has_base_update():
             vbu = self.get_base_update_var()
-            xbu = self.get_base_update_xpr()
-            return "; " + str(vbu) + " := " + str(xbu)
+            xbu = self.get_base_update_cxpr()
+            return "; wbu: " + str(vbu) + " := " + str(xbu)
         else:
             return ""
 

chb/arm/opcodes/ARMBranch.py

@@ -137,13 +137,17 @@ def is_cfcond_ok(self) -> bool:
 
     @property
     def xtgt(self) -> "XXpr":
-        index = 1 if self.is_unconditional else 4
-        return self.xpr(index, "xtgt")
+        if self.is_unconditional or (not self.has_branch_conditions()):
+            return self.xpr(1, "xtgt")
+        else:
+            return self.xpr(4, "xtgt")
 
     @property
     def is_xtgt_ok(self) -> bool:
-        index = 1 if self.is_unconditional else 4
-        return self.is_xpr_ok(index)
+        if self.is_unconditional or (not self.has_branch_conditions()):
+            return self.is_xpr_ok(1)
+        else:
+            return self.is_xpr_ok(4)
 
     @property
     def annotation(self) -> str:
@@ -338,7 +342,7 @@ def default(condition: XXpr) -> AST.ASTExpr:
                         condition = xd.txpr
             else:
                 chklogger.logger.error(
-                    "Bxx: conditional branch without branch conditions "
+                    "Bcc: conditional branch without branch conditions "
                     + "at address %s", iaddr)
                 hl_astcond = astree.mk_temp_lval_expression()
                 return (hl_astcond, ll_astcond)

chb/arm/opcodes/ARMLoadRegister.py

@@ -322,43 +322,9 @@ def has_cast() -> bool:
             ll_assigns: List[AST.ASTInstruction] = [ll_assign, ll_addr_assign]
 
             basereg = xd.get_base_update_var()
-            newaddr = xd.get_base_update_xpr()
+            newaddr = xd.get_base_update_cxpr()
             hl_addr_lhs = XU.xvariable_to_ast_lval(basereg, xdata, iaddr, astree)
-
-            hl_addr_lhs_type = hl_addr_lhs.ctype(astree.ctyper)
-            if hl_addr_lhs_type is not None and len(xdata.ints) > 0:
-                if hl_addr_lhs_type.is_pointer:
-                    addrtype = cast(AST.ASTTypPtr, hl_addr_lhs_type)
-                    tgttyp = addrtype.tgttyp
-                    tgttypsize = astree.type_size_in_bytes(tgttyp)
-                    if tgttypsize is not None:
-                        incr = xdata.ints[0]
-                        ptrincr = incr // tgttypsize
-                        hl_addr_rhs = astree.mk_binary_op(
-                            "plus",
-                            astree.mk_lval_expression(hl_addr_lhs),
-                            astree.mk_integer_constant(ptrincr))
-                    else:
-                        hl_addr_rhs = XU.xxpr_to_ast_def_expr(
-                            newaddr, xdata, iaddr, astree)
-                        chklogger.logger.warning(
-                            "LDR address adjustment not scaled due to missing "
-                            + "size of pointer target type %s at address %s",
-                            str(tgttyp), iaddr)
-                else:
-                    hl_addr_rhs = XU.xxpr_to_ast_def_expr(
-                        newaddr, xdata, iaddr, astree)
-                    chklogger.logger.warning(
-                        "LDR address adjustment not scaled due to unexpected "
-                        + "address type: %s at address %s",
-                        str(hl_addr_lhs_type), iaddr)
-            else:
-                hl_addr_rhs = XU.xxpr_to_ast_def_expr(
-                    newaddr, xdata, iaddr, astree)
-                chklogger.logger.warning(
-                    "LDR address adjustment not scaled due to lack of type "
-                    + "information at address %s",
-                    iaddr)
+            hl_addr_rhs = XU.xxpr_to_ast_def_expr(newaddr, xdata, iaddr, astree)
 
             hl_addr_assign = astree.mk_assign(
                 hl_addr_lhs,
@@ -368,9 +334,6 @@ def has_cast() -> bool:
                 annotations=annotations)
             hl_assigns: List[AST.ASTInstruction] = [hl_assign, hl_addr_assign]
 
-            # Note: work-around for deficiency in def-use propagation
-            astree.add_expose_instruction(hl_addr_assign.instrid)
-
             astree.add_instr_mapping(hl_addr_assign, ll_addr_assign)
             astree.add_instr_address(hl_addr_assign, [iaddr])
             astree.add_expr_mapping(hl_addr_rhs, ll_addr_rhs)