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support for conditional return instruction
1 parent c76333b commit 6f6e1ea

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8 files changed

+50
-5
lines changed

8 files changed

+50
-5
lines changed

chb/arm/ARMInstruction.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,10 @@ def is_store_instruction(self) -> bool:
171171
def is_return_instruction(self) -> bool:
172172
return self.opcode.is_return_instruction(self.xdata)
173173

174+
@property
175+
def is_conditional_return_instruction(self) -> bool:
176+
return self.opcode.is_conditional_return_instruction(self.xdata)
177+
174178
@property
175179
def is_nop_instruction(self) -> bool:
176180
return self.opcode.is_nop_instruction(self.xdata)

chb/arm/ARMOpcode.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -522,6 +522,9 @@ def is_branch_instruction(self) -> bool:
522522
def is_return_instruction(self, xdata: InstrXData) -> bool:
523523
return False
524524

525+
def is_conditional_return_instruction(self, xdata: InstrXData) -> bool:
526+
return False
527+
525528
def return_value(self, xdata: InstrXData) -> Optional[XXpr]:
526529
return None
527530

chb/arm/opcodes/ARMLoadRegisterSignedByte.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -126,6 +126,10 @@ def __init__(self, d: "ARMDictionary", ixval: IndexedTableValue) -> None:
126126
def operands(self) -> List[ARMOperand]:
127127
return [self.armd.arm_operand(self.args[i]) for i in [0, 3]]
128128

129+
@property
130+
def opargs(self) -> List[ARMOperand]:
131+
return [self.armd.arm_operand(self.args[i]) for i in [0, 1, 2, 3]]
132+
129133
def is_load_instruction(self, xdata: InstrXData) -> bool:
130134
return True
131135

chb/arm/opcodes/ARMLoadRegisterSignedHalfword.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,7 @@ def ast_prov(
183183
rhs, xdata, iaddr, astree, memaddr=xaddr, size=2)
184184

185185
elif xd.is_xrmem_unknown and xd.is_address_known:
186+
lhs = xd.vrt
186187
xaddr = xd.xaddr
187188
hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
188189
hl_rhs = XU.xmemory_dereference_lval_expr(

chb/arm/opcodes/ARMMove.py

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,18 @@ def cresult(self) -> "XXpr":
9090
def is_cresult_ok(self) -> bool:
9191
return self.is_cxpr_ok(0)
9292

93+
def has_instruction_condition(self) -> bool:
94+
return self.xdata.has_instruction_condition()
95+
96+
def get_instruction_condition(self) -> "XXpr":
97+
return self.xdata.get_instruction_condition()
98+
99+
def has_valid_instruction_c_condition(self) -> bool:
100+
return self.xdata.has_valid_instruction_c_condition()
101+
102+
def get_instruction_c_condition(self) -> "XXpr":
103+
return self.xdata.get_instruction_c_condition()
104+
93105
@property
94106
def annotation(self) -> str:
95107
if self.xdata.instruction_is_subsumed():

chb/arm/opcodes/ARMPop.py

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,11 @@ def operandstring(self) -> str:
196196
def is_return_instruction(self, xdata: InstrXData) -> bool:
197197
return ARMPopXData(xdata).has_return_xpr()
198198

199+
def is_conditional_return_instruction(self, xdata: InstrXData) -> bool:
200+
if self.is_return_instruction(xdata):
201+
return xdata.has_instruction_condition()
202+
return False
203+
199204
def return_value(self, xdata: InstrXData) -> Optional[XXpr]:
200205
xd = ARMPopXData(xdata)
201206
if xd.has_return_xpr():
@@ -222,10 +227,13 @@ def ast_condition_prov(
222227
ll_astcond = self.ast_cc_expr(astree)
223228

224229
if xdata.has_instruction_condition():
230+
pcond = xdata.get_instruction_condition()
231+
'''
225232
if reverse:
226233
pcond = xdata.xprs[(2 * len(xdata.vars)) + 3]
227234
else:
228235
pcond = xdata.xprs[(2 * len(xdata.vars)) + 2]
236+
'''
229237
hl_astcond = XU.xxpr_to_ast_def_expr(pcond, xdata, iaddr, astree)
230238

231239
astree.add_expr_mapping(hl_astcond, ll_astcond)

chb/arm/opcodes/opcodes_covered.json

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -815,7 +815,8 @@
815815
{
816816
"T": "A1",
817817
"E": "<cc><6>PUDW1<rn><vd><11><-imm7>1",
818-
"D": "Y"
818+
"D": "Y",
819+
"U": ["210b90ec"]
819820
},
820821
{
821822
"T": "A2",
@@ -843,7 +844,8 @@
843844
{
844845
"T": "A1",
845846
"E": "<cc><6>01D00<rn><vd><11><-imm7>1",
846-
"D": "Y"
847+
"D": "Y",
848+
"U": ["210b80ec"]
847849
},
848850
{
849851
"T": "A1-wb",
@@ -895,7 +897,10 @@
895897
"U": ["02a1f0ec"]
896898
},
897899
{
898-
"T": "A2"
900+
"T": "A2",
901+
"E": "<15><6>PUDW1<rn><cd><cp><-imm8->",
902+
"D": "Y",
903+
"U": ["0181b0fc"]
899904
},
900905
{
901906
"T": "T1",
@@ -2662,7 +2667,9 @@
26622667
"all": [
26632668
{
26642669
"T": "A2",
2665-
"E": "<15>110PU0W0<rn><cd><cp><-imm8->"
2670+
"E": "<15>110PU0W0<rn><cd><cp><-imm8->",
2671+
"D": "Y",
2672+
"U": ["0181a0fc"]
26662673
},
26672674
{
26682675
"T": "T2",
@@ -2692,7 +2699,9 @@
26922699
"all": [
26932700
{
26942701
"T": "A1",
2695-
"E": "<cc>110PU1W0<rn><cd><cp><-imm8->"
2702+
"E": "<cc>110PU1W0<rn><cd><cp><-imm8->",
2703+
"D": "Y",
2704+
"U": ["0201e0ec"]
26962705
},
26972706
{
26982707
"T": "T1",

chb/astinterface/ASTInterfaceBasicBlock.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,10 @@ def trampoline_block_instructions(
119119
def has_return(self) -> bool:
120120
return self.basicblock.has_return
121121

122+
@property
123+
def has_conditional_return(self) -> bool:
124+
return self.basicblock.has_conditional_return
125+
122126
@property
123127
def last_instruction(self) -> ASTInterfaceInstruction:
124128
bb_lastinstr = self.basicblock.last_instruction

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