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ARM:STM: update astprov for error values
1 parent 62e9034 commit 7eae864

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2 files changed

+29
-18
lines changed

2 files changed

+29
-18
lines changed

chb/app/CHVersion.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
chbversion: str = "0.3.0-20250314"
1+
chbversion: str = "0.3.0-20250318"

chb/arm/opcodes/ARMStoreMultipleIncrementAfter.py

Lines changed: 28 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,8 @@
4545

4646
if TYPE_CHECKING:
4747
from chb.arm.ARMDictionary import ARMDictionary
48-
from chb.invariants.VAssemblyVariable import VRegisterVariable
48+
from chb.invariants.VAssemblyVariable import (
49+
VRegisterVariable, VMemoryVariable)
4950
from chb.invariants.XVariable import XVariable
5051
from chb.invariants.XXpr import XXpr, XprConstant, XprVariable
5152

@@ -417,28 +418,23 @@ def ast_prov(
417418
if xdata.instruction_subsumes():
418419
return self.ast_prov_ldmstmcopy(astree, iaddr, bytestring, xdata)
419420

420-
else:
421+
xd = ARMStoreMultipleIncrementAfterXData(xdata)
422+
if not xd.is_ok:
421423
chklogger.logger.error(
422-
"AST conversion of STM not yet supported at address %s",
423-
iaddr)
424+
"STM: Error value encountered at address %s", iaddr)
424425
return ([], [])
425426

426-
regcount = len(xdata.reachingdefs) - 1
427+
annotations: List[str] = [iaddr, "STM"]
428+
429+
'''
427430
baselhs = xdata.vars[0]
428-
memlhss = xdata.vars[1:]
429431
baserhs = xdata.xprs[0]
430432
baseresult = xdata.xprs[1]
431433
baseresultr = xdata.xprs[2]
432-
regrhss = xdata.xprs[3:3 + regcount]
433-
#rregrhss = xdata.xprs[3 + regcount:3 + (2 * regcount)]
434434
baserdef = xdata.reachingdefs[0]
435-
regrdefs = xdata.reachingdefs[1:]
436435
baseuses = xdata.defuses[0]
437-
memuses = xdata.defuses[1:]
438436
baseuseshigh = xdata.defuseshigh[0]
439-
memuseshigh = xdata.defuseshigh[1:]
440-
441-
annotations: List[str] = [iaddr, "STMIA"]
437+
'''
442438

443439
# low-level assignments
444440

@@ -448,6 +444,12 @@ def ast_prov(
448444
(baselval, _, _) = self.opargs[0].ast_lvalue(astree)
449445
(baserval, _, _) = self.opargs[0].ast_rvalue(astree)
450446

447+
memlhss = xd.memlhss
448+
regrhss = xd.rhss
449+
regrdefs = xdata.reachingdefs[1:]
450+
memuses = xdata.defuses[1:]
451+
memuseshigh = xdata.defuseshigh[1:]
452+
451453
regsop = self.opargs[1]
452454
registers = regsop.registers
453455
base_offset = 0
@@ -469,10 +471,11 @@ def ast_prov(
469471

470472
# high-level assignments
471473

472-
lhs = memlhss[i]
473-
rhs = regrhss[i]
474-
hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
475-
hl_rhs = XU.xxpr_to_ast_def_expr(rhs, xdata, iaddr, astree)
474+
memlhs = memlhss[i]
475+
regrhs = regrhss[i]
476+
477+
hl_lhs = XU.xvariable_to_ast_lval(memlhs, xdata, iaddr, astree)
478+
hl_rhs = XU.xxpr_to_ast_def_expr(regrhs, xdata, iaddr, astree)
476479
hl_assign = astree.mk_assign(
477480
hl_lhs,
478481
hl_rhs,
@@ -491,6 +494,13 @@ def ast_prov(
491494

492495
base_offset += 4
493496

497+
if (
498+
(memlhs.is_memory_variable
499+
and cast("VMemoryVariable",
500+
memlhs.denotation).base.is_basevar)):
501+
astree.add_expose_instruction(hl_assign.instrid)
502+
503+
'''
494504
if self.writeback:
495505
496506
# low-level base assignment
@@ -528,5 +538,6 @@ def ast_prov(
528538
astree.add_expr_reachingdefs(ll_base_rhs, [baserdef])
529539
astree.add_lval_defuses(hl_base_lhs, baseuses)
530540
astree.add_lval_defuses_high(hl_base_lhs, baseuseshigh)
541+
'''
531542

532543
return (hl_instrs, ll_instrs)

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