ARM: updates for result types / c expressions

Author: sipma

chb/arm/opcodes/ARMBitwiseAnd.py

@@ -160,10 +160,15 @@ def operands(self) -> List[ARMOperand]:
     def opargs(self) -> List[ARMOperand]:
         return [self.armd.arm_operand(i) for i in self.args[1:-1]]
 
+    @property
+    def writeback(self) -> bool:
+        return self.args[0] == 1
+
     def mnemonic_extension(self) -> str:
+        wb = "S" if self.writeback else ""
         cc = ARMOpcode.mnemonic_extension(self)
         wide = ".W" if self.args[4] == 1 else ""
-        return cc + wide
+        return wb + cc + wide
 
     def annotation(self, xdata: InstrXData) -> str:
         xd = ARMBitwiseAndXData(xdata)

chb/arm/opcodes/ARMBranchExchange.py

@@ -89,18 +89,6 @@ def has_creturnval(self) -> bool:
     def creturnval(self) -> "XXpr":
         return self.xdata.get_return_cxpr()
 
-    def has_instruction_condition(self) -> bool:
-        return self.xdata.has_instruction_condition()
-
-    def get_instruction_condition(self) -> "XXpr":
-        return self.xdata.get_instruction_condition()
-
-    def has_valid_instruction_c_condition(self) -> bool:
-        return self.xdata.has_valid_instruction_c_condition()
-
-    def get_instruction_c_condition(self) -> "XXpr":
-        return self.xdata.get_instruction_c_condition()
-
     @property
     def annotation(self) -> str:
         if self.xdata.is_bx_call:

chb/arm/opcodes/ARMByteReversePackedHalfword.py

@@ -38,9 +38,11 @@
 from chb.astinterface.ASTInterface import ASTInterface
 
 import chb.invariants.XXprUtil as XU
-import chb.util.fileutil as UF
 
+import chb.util.fileutil as UF
 from chb.util.IndexedTable import IndexedTableValue
+from chb.util.loggingutil import chklogger
+
 
 if TYPE_CHECKING:
     from chb.arm.ARMDictionary import ARMDictionary
@@ -155,11 +157,7 @@ def ast_prov(
 
         annotations: List[str] = [iaddr, "REV16"]
 
-        lhs = xdata.vars[0]
-        rhs = xdata.xprs[0]
-        rdefs = xdata.reachingdefs
-        defuses = xdata.defuses
-        defuseshigh = xdata.defuseshigh
+        # low-level assignment
 
         (ll_lhs, _, _) = self.opargs[0].ast_lvalue(astree)
         (ll_rhs, _, _) = self.opargs[1].ast_rvalue(astree)
@@ -171,30 +169,23 @@ def ast_prov(
             iaddr=iaddr,
             bytestring=bytestring)
 
-        lhsasts = XU.xvariable_to_ast_lvals(lhs, xdata, astree)
-        if len(lhsasts) == 0:
-            raise UF.CHBError(
-                "ByteReversePatckedHalfword (REV16): no lval found")
+        # high-level assignment
 
-        if len(lhsasts) > 1:
-            raise UF.CHBError(
-                "ByteReversePackedHalfword (REV16): multiple lvals in ast: "
-                + ", ".join(str(v) for v in lhsasts))
-
-        hl_lhs = lhsasts[0]
+        xd = ARMByteReversePackedHalfwordXData(xdata)
+        if not xd.is_ok:
+            chklogger.logger.error(
+                "Encountered error value at address %s", iaddr)
+            return ([], [])
 
-        rhsasts = XU.xxpr_to_ast_def_exprs(rhs, xdata, iaddr, astree)
-        if len(rhsasts) == 0:
-            raise UF.CHBError(
-                "ByteReversePackedHalfword (REV16): no argument value found")
+        lhs = xd.vrd
+        rhs = xd.xxrm
 
-        if len(rhsasts) > 1:
-            raise UF.CHBError(
-                "ByteReversePackedHalfword (REV16): "
-                + "multiple argument values in asts: "
-                + ", ".join(str(x) for x in rhsasts))
+        rdefs = xdata.reachingdefs
+        defuses = xdata.defuses
+        defuseshigh = xdata.defuseshigh
 
-        hl_rhs = rhsasts[0]
+        hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
+        hl_rhs = XU.xxpr_to_ast_def_expr(rhs, xdata, iaddr, astree)
 
         if astree.has_variable_intro(iaddr):
             vname = astree.get_variable_intro(iaddr)

chb/arm/opcodes/ARMByteReverseWord.py

@@ -39,8 +39,9 @@
 import chb.invariants.XXprUtil as XU
 
 import chb.util.fileutil as UF
-
 from chb.util.IndexedTable import IndexedTableValue
+from chb.util.loggingutil import chklogger
+
 
 if TYPE_CHECKING:
     from chb.arm.ARMDictionary import ARMDictionary
@@ -157,11 +158,7 @@ def ast_prov(
 
         annotations: List[str] = [iaddr, "REV"]
 
-        lhs = xdata.vars[0]
-        rhs = xdata.xprs[0]
-        rdefs = xdata.reachingdefs
-        defuses = xdata.defuses
-        defuseshigh = xdata.defuseshigh
+        # low-level assignment
 
         (ll_lhs, _, _) = self.opargs[0].ast_lvalue(astree)
         (ll_rhs, _, _) = self.opargs[1].ast_rvalue(astree)
@@ -173,27 +170,22 @@ def ast_prov(
             iaddr=iaddr,
             bytestring=bytestring)
 
-        lhsasts = XU.xvariable_to_ast_lvals(lhs, xdata, astree)
-        if len(lhsasts) == 0:
-            raise UF.CHBError("ByteReverseWord (REV): no lval found")
+        # high-level assignment
 
-        if len(lhsasts) > 1:
-            raise UF.CHBError(
-                "ByteReverseWord (REV): multiple lvals in ast: "
-                + ", ".join(str(v) for v in lhsasts))
-
-        hl_lhs = lhsasts[0]
+        xd = ARMByteReverseWordXData(xdata)
+        if not xd.is_ok:
+            chklogger.logger.error(
+                "REV: Encountered error value at address %s", iaddr)
 
-        rhsasts = XU.xxpr_to_ast_def_exprs(rhs, xdata, iaddr, astree)
-        if len(rhsasts) == 0:
-            raise UF.CHBError("ByteReverseWord (REV): no argument value found")
+        lhs = xd.vrd
+        rhs = xd.xxrn
 
-        if len(rhsasts) > 1:
-            raise UF.CHBError(
-                "ByteReverseWord (REV): multiple argument values in asts: "
-                + ", ".join(str(x) for x in rhsasts))
+        rdefs = xdata.reachingdefs
+        defuses = xdata.defuses
+        defuseshigh = xdata.defuseshigh
 
-        hl_rhs = rhsasts[0]
+        hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
+        hl_rhs = XU.xxpr_to_ast_def_expr(rhs, xdata, iaddr, astree)
 
         if astree.has_variable_intro(iaddr):
             vname = astree.get_variable_intro(iaddr)

chb/arm/opcodes/ARMLoadMultipleIncrementAfter.py

@@ -193,7 +193,7 @@ def annotation(self) -> str:
         else:
             pairs = []
         if len(pairs) > 0:
-            assigns = "; ".join(str(v) + " := " + str(x) for (x, v) in pairs)
+            assigns = "; ".join(str(v) + " := " + str(x) for (v, x) in pairs)
         else:
             assigns = "unknown rhs memory"
         wbu = self.writeback_update()

chb/arm/opcodes/ARMLoadRegister.py

@@ -152,6 +152,8 @@ def annotation(self) -> str:
                 str(self.vrt) + " := *(" + str(self.xaddr) + ")" + cx + caddr)
         else:
             assignment = "Error value"
+        pcwarning = "**indirect call** " if str(self.vrt) == "PC" else ""
+        assignment = pcwarning + assignment
         return self.add_instruction_condition(assignment) + wbu
 
 
@@ -251,6 +253,12 @@ def has_cast() -> bool:
 
         lhs = xd.vrt
 
+        if str(lhs) == "PC":
+            chklogger.logger.error(
+                "LDR: Indirect call via Load to PC not yet handled at %s",
+                iaddr)
+            return ([], (ll_pre + [ll_assign] + ll_post))
+
         if xd.is_ok:
             rhs = xd.cxrmem
             rhsval = None if has_cast() else xd.cxrmem

chb/arm/opcodes/ARMLogicalShiftLeft.py

@@ -49,6 +49,19 @@
 
 
 class ARMLogicalShiftLeftXData(ARMOpcodeXData):
+    """Data format:
+    - variables:
+    0: vrd
+
+    - expressions:
+    0: xrn
+    1: xrm
+    2: result
+    3: rresult (result rewritten)
+
+    - c expresions:
+    0: cresult
+    """
 
     def __init__(self, xdata: InstrXData) -> None:
         ARMOpcodeXData.__init__(self, xdata)
@@ -69,18 +82,41 @@ def xrm(self) -> "XXpr":
     def result(self) -> "XXpr":
         return self.xpr(2, "result")
 
+    @property
+    def is_result_ok(self) -> bool:
+        return self.is_xpr_ok(2)
+
     @property
     def rresult(self) -> "XXpr":
         return self.xpr(3, "rresult")
 
+    @property
+    def is_rresult_ok(self) -> bool:
+        return self.is_xpr_ok(3)
+
+    @property
+    def cresult(self) -> "XXpr":
+        return self.cxpr(0, "cresult")
+
+    @property
+    def is_cresult_ok(self) -> bool:
+        return self.is_cxpr_ok(0)
+
     @property
     def result_simplified(self) -> str:
-        return simplify_result(
-            self.xdata.args[3], self.xdata.args[4], self.result, self.rresult)
+        if self.is_result_ok and self.is_rresult_ok:
+            return simplify_result(
+                self.xdata.args[3], self.xdata.args[4], self.result, self.rresult)
+        else:
+            return str(self.xrn) + " << " + str(self.xrm)
 
     @property
     def annotation(self) -> str:
-        assignment = str(self.vrd) + " := " + self.result_simplified
+        cresult = (
+            " (C: "
+            + (str(self.cresult) if self.is_cresult_ok else "None")
+            + ")")
+        assignment = str(self.vrd) + " := " + self.result_simplified + cresult
         return self.add_instruction_condition(assignment)
 
 
@@ -156,10 +192,7 @@ def lsl_xdata(self, xdata: InstrXData) -> ARMLogicalShiftLeftXData:
 
     def annotation(self, xdata: InstrXData) -> str:
         xd = ARMLogicalShiftLeftXData(xdata)
-        if xd.is_ok:
-            return xd.annotation
-        else:
-            return "Error value"
+        return xd.annotation
 
     def ast_prov(
             self,
@@ -185,24 +218,35 @@ def ast_prov(
             bytestring=bytestring,
             annotations=annotations)
 
+        rdefs = xdata.reachingdefs
+
+        astree.add_expr_reachingdefs(ll_rhs1, [rdefs[0]])
+        astree.add_expr_reachingdefs(ll_rhs2, [rdefs[1]])
+
         # high-level assignment
 
         xd = ARMLogicalShiftLeftXData(xdata)
-        if not xd.is_ok:
+
+        if xd.is_cresult_ok and xd.is_rresult_ok:
+            rhs = xd.cresult
+
+        elif xd.is_rresult_ok:
+            rhs = xd.rresult
+
+        elif xd.is_result_ok:
+            rhs = xd.result
+
+        else:
             chklogger.logger.error(
-                "Encountered error value at address %s", iaddr)
-            return ([], [])
+                "LSL: Encountered error value for rhs address %s", iaddr)
+            return ([], [ll_assign])
 
         lhs = xd.vrd
-        rhs1 = xd.xrn
-        rhs2 = xd.xrm
-        rresult = xd.rresult
-        rdefs = xdata.reachingdefs
         defuses = xdata.defuses
         defuseshigh = xdata.defuseshigh
 
         hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
-        hl_rhs = XU.xxpr_to_ast_def_expr(rresult, xdata, iaddr, astree)
+        hl_rhs = XU.xxpr_to_ast_def_expr(rhs, xdata, iaddr, astree)
 
         hl_assign = astree.mk_assign(
             hl_lhs,
@@ -216,8 +260,6 @@ def ast_prov(
         astree.add_expr_mapping(hl_rhs, ll_rhs)
         astree.add_lval_mapping(hl_lhs, ll_lhs)
         astree.add_expr_reachingdefs(ll_rhs, [rdefs[0], rdefs[1]])
-        astree.add_expr_reachingdefs(ll_rhs1, [rdefs[0]])
-        astree.add_expr_reachingdefs(ll_rhs2, [rdefs[1]])
         astree.add_expr_reachingdefs(hl_rhs, rdefs[2:])
         astree.add_lval_defuses(hl_lhs, defuses[0])
         astree.add_lval_defuses_high(hl_lhs, defuseshigh[0])