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ARM:XDATA: add check for complex lhs
1 parent fe7bb2d commit b1ab225

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3 files changed

+25
-8
lines changed

3 files changed

+25
-8
lines changed

chb/arm/opcodes/ARMStoreRegister.py

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,10 @@ def ast_prov(
239239
hl_lhs = XU.xmemory_dereference_lval(memaddr, xdata, iaddr, astree)
240240

241241
else:
242-
chklogger.logger.error("Error value encountered at %s", iaddr)
242+
chklogger.logger.error(
243+
"STR: Lhs lval and address both have error values: skipping "
244+
"store instruction at address %s",
245+
iaddr)
243246
return ([], [])
244247

245248
rhs = xd.xxrt

chb/arm/opcodes/ARMStoreRegisterByte.py

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,9 @@ def ast_prov(
199199

200200
else:
201201
chklogger.logger.error(
202-
"Encountered error value at address %s", iaddr)
202+
"STRB: Lhs lval and address both have error values: skipping "
203+
+ "store instruction at address %s",
204+
iaddr)
203205
return ([], [])
204206

205207
rhs = xd.xxrt
@@ -222,9 +224,13 @@ def ast_prov(
222224
bytestring=bytestring,
223225
annotations=annotations)
224226

225-
# to highlight missing info, expose in the lifting store instructions
226-
# that are unresolved
227-
if xd.is_vmem_unknown:
227+
# Currently def-use info does not properly account for assignments
228+
# to variables that are part of a struct or array variable, so these
229+
# assignments must be explicitly forced to appear in the lifting
230+
if (
231+
xd.is_vmem_unknown
232+
or hl_lhs.offset.is_index_offset
233+
or hl_lhs.offset.is_field_offset):
228234
astree.add_expose_instruction(hl_assign.instrid)
229235

230236
astree.add_instr_mapping(hl_assign, ll_assign)

chb/arm/opcodes/ARMStoreRegisterHalfword.py

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -194,13 +194,14 @@ def ast_prov(
194194
lhs, xdata, iaddr, astree, memaddr=memaddr)
195195

196196
elif xd.is_vmem_unknown and xd.is_address_known:
197-
lhs = None
198197
memaddr = xd.xaddr
199198
hl_lhs = XU.xmemory_dereference_lval(memaddr, xdata, iaddr, astree)
200199

201200
else:
202201
chklogger.logger.error(
203-
"Encountered error value at address %s", iaddr)
202+
"STRH: Lhs lval and address both have error values: skipping "
203+
+ "store instruction at address %s",
204+
iaddr)
204205
return ([], [])
205206

206207
rhs = xd.xxrt
@@ -217,8 +218,15 @@ def ast_prov(
217218
bytestring=bytestring,
218219
annotations=annotations)
219220

220-
if lhs is not None and lhs.is_tmp:
221+
# Currently def-use info does not properly account for assignments
222+
# to variables that are part of a struct or array variable, so these
223+
# assignments must be explicitly forced to appear in the lifting
224+
if (
225+
xd.is_vmem_unknown
226+
or hl_lhs.offset.is_index_offset
227+
or hl_lhs.offset.is_field_offset):
221228
astree.add_expose_instruction(hl_assign.instrid)
229+
222230
astree.add_instr_mapping(hl_assign, ll_assign)
223231
astree.add_instr_address(hl_assign, [iaddr])
224232
astree.add_expr_mapping(hl_rhs, ll_rhs)

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