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ARM: updates of vector instructions for result types
1 parent 12b16c3 commit c75304c

17 files changed

+770
-166
lines changed

‎chb/arm/opcodes/ARMBitFieldInsert.py‎

Lines changed: 35 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,18 @@
5353
class ARMBitFieldInsertXData(ARMOpcodeXData):
5454
"""BFI <rd> <rn>"""
5555

56-
def __init__(self, xdata: InstrXData) -> None:
56+
def __init__(self, xdata: InstrXData, lsb: int, width: int) -> None:
5757
ARMOpcodeXData.__init__(self, xdata)
58+
self._lsb = lsb
59+
self._width = width
60+
61+
@property
62+
def lsb(self) -> int:
63+
return self._lsb
64+
65+
@property
66+
def width(self) -> int:
67+
return self._width
5868

5969
@property
6070
def vrd(self) -> "XVariable":
@@ -68,6 +78,23 @@ def xrd(self) -> "XXpr":
6878
def xrn(self) -> "XXpr":
6979
return self.xpr(1, "xrn")
7080

81+
@property
82+
def annotation(self) -> str:
83+
lhs = str(self.vrd)
84+
rhs1 = str(self.xrd)
85+
rhs2 = str(self.xrn)
86+
assign = (
87+
lhs
88+
+ " := bit-field-insert("
89+
+ rhs1
90+
+ ", "
91+
+ rhs2
92+
+ ", lsb:"
93+
+ str(self.lsb)
94+
+ ", width:"
95+
+ str(self.width))
96+
return self.add_instruction_condition(assign)
97+
7198

7299
@armregistry.register_tag("BFI", ARMOpcode)
73100
class ARMBitFieldInsert(ARMOpcode):
@@ -123,30 +150,8 @@ def width(self) -> int:
123150
return self.args[2]
124151

125152
def annotation(self, xdata: InstrXData) -> str:
126-
xd = ARMBitFieldInsertXData(xdata)
127-
if xd.is_ok:
128-
lhs = str(xd.vrd)
129-
rhs1 = str(xd.xrd)
130-
rhs2 = str(xd.xrn)
131-
assignment = (
132-
lhs
133-
+ " := bit-field-insert("
134-
+ rhs1
135-
+ ", "
136-
+ rhs2
137-
+ ", lsb:"
138-
+ str(self.lsb)
139-
+ ", width:"
140-
+ str(self.width))
141-
if xdata.has_unknown_instruction_condition():
142-
return "if ? then " + assignment
143-
elif xdata.has_instruction_condition():
144-
c = str(xdata.xprs[1])
145-
return "if " + c + " then " + assignment
146-
else:
147-
return assignment
148-
else:
149-
return "Error value"
153+
xd = ARMBitFieldInsertXData(xdata, self.lsb, self.width)
154+
return xd.annotation
150155

151156
def ast_prov(
152157
self,
@@ -168,9 +173,11 @@ def ast_prov(
168173

169174
return ([], [nopinstr])
170175

171-
lhs = xdata.vars[0]
172-
rhs1 = xdata.xprs[0]
173-
rhs2 = xdata.xprs[1]
176+
xd = ARMBitFieldInsertXData(xdata, self.lsb, self.width)
177+
178+
lhs = xd.vrd
179+
rhs1 = xd.xrd
180+
rhs2 = xd.xrn
174181
rdefs = xdata.reachingdefs
175182
defuses = xdata.defuses
176183
defuseshigh = xdata.defuseshigh

‎chb/arm/opcodes/ARMByteReversePackedHalfword.py‎

Lines changed: 35 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# ------------------------------------------------------------------------------
55
# The MIT License (MIT)
66
#
7-
# Copyright (c) 2021-2023 Aarno Labs LLC
7+
# Copyright (c) 2021-2025 Aarno Labs LLC
88
#
99
# Permission is hereby granted, free of charge, to any person obtaining a copy
1010
# of this software and associated documentation files (the "Software"), to deal
@@ -30,7 +30,7 @@
3030
from chb.app.InstrXData import InstrXData
3131

3232
from chb.arm.ARMDictionaryRecord import armregistry
33-
from chb.arm.ARMOpcode import ARMOpcode, simplify_result
33+
from chb.arm.ARMOpcode import ARMOpcode, ARMOpcodeXData, simplify_result
3434
from chb.arm.ARMOperand import ARMOperand
3535

3636
from chb.ast.ARMIntrinsics import ARMIntrinsics
@@ -44,6 +44,37 @@
4444

4545
if TYPE_CHECKING:
4646
from chb.arm.ARMDictionary import ARMDictionary
47+
from chb.invariants.XVariable import XVariable
48+
from chb.invariants.XXpr import XprCompound, XprConstant, XXpr
49+
50+
51+
class ARMByteReversePackedHalfwordXData(ARMOpcodeXData):
52+
"""REV16 <rd> <rm>"""
53+
54+
def __init__(self, xdata: InstrXData) -> None:
55+
ARMOpcodeXData.__init__(self, xdata)
56+
57+
@property
58+
def vrd(self) -> "XVariable":
59+
return self.var(0, "vrd")
60+
61+
@property
62+
def xrm(self) -> "XXpr":
63+
return self.xpr(0, "xrm")
64+
65+
@property
66+
def xxrm(self) -> "XXpr":
67+
return self.xpr(1, "xxrm")
68+
69+
@property
70+
def annotation(self) -> str:
71+
if self.is_ok:
72+
lhs = str(self.vrd)
73+
rhs = str(self.xxrm)
74+
assign = lhs + " := __rev16(" + str(rhs) + ") intrinsic"
75+
return self.add_instruction_condition(assign)
76+
else:
77+
return "REV16: error"
4778

4879

4980
@armregistry.register_tag("REV16", ARMOpcode)
@@ -89,16 +120,8 @@ def opargs(self) -> List[ARMOperand]:
89120
return [self.armd.arm_operand(i) for i in self.args[:-1]]
90121

91122
def annotation(self, xdata: InstrXData) -> str:
92-
lhs = str(xdata.vars[0])
93-
rhs = str(xdata.xprs[1])
94-
assignment = lhs + " := __rev16(" + str(rhs) + ") intrinsic"
95-
if xdata.has_unknown_instruction_condition():
96-
return "if ? then " + assignment
97-
elif xdata.has_instruction_condition():
98-
c = str(xdata.xprs[1])
99-
return "if " + c + " then " + assignment
100-
else:
101-
return assignment
123+
xd = ARMByteReversePackedHalfwordXData(xdata)
124+
return xd.annotation
102125

103126
# --------------------------------------------------------------------------
104127
# Operation

‎chb/arm/opcodes/ARMMove.py‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,10 @@ def is_cresult_ok(self) -> bool:
9292

9393
@property
9494
def annotation(self) -> str:
95+
if self.xdata.instruction_is_subsumed():
96+
return "subsumed by " + self.xdata.subsumed_by()
97+
if self.xdata.instruction_subsumes():
98+
return "subsumes " + ", ".join(self.xdata.subsumes())
9599
cx = " (C: " + (str(self.cresult) if self.is_cresult_ok else "None") + ")"
96100
rhs = str(self.result) if self.is_result_ok else str(self.xrm)
97101
assignment = str(self.vrd) + " := " + rhs + cx

‎chb/arm/opcodes/ARMSignedBitFieldExtract.py‎

Lines changed: 39 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# ------------------------------------------------------------------------------
55
# The MIT License (MIT)
66
#
7-
# Copyright (c) 2021-2022 Aarno Labs LLC
7+
# Copyright (c) 2021-2025 Aarno Labs LLC
88
#
99
# Permission is hereby granted, free of charge, to any person obtaining a copy
1010
# of this software and associated documentation files (the "Software"), to deal
@@ -25,20 +25,50 @@
2525
# SOFTWARE.
2626
# ------------------------------------------------------------------------------
2727

28-
from typing import List, TYPE_CHECKING
28+
from typing import List, Tuple, TYPE_CHECKING
2929

3030
from chb.app.InstrXData import InstrXData
3131

3232
from chb.arm.ARMDictionaryRecord import armregistry
33-
from chb.arm.ARMOpcode import ARMOpcode, simplify_result
33+
from chb.arm.ARMOpcode import ARMOpcode, ARMOpcodeXData, simplify_result
3434
from chb.arm.ARMOperand import ARMOperand
3535

3636
import chb.util.fileutil as UF
37-
3837
from chb.util.IndexedTable import IndexedTableValue
38+
from chb.util.loggingutil import chklogger
3939

4040
if TYPE_CHECKING:
4141
from chb.arm.ARMDictionary import ARMDictionary
42+
from chb.invariants.XVariable import XVariable
43+
from chb.invariants.XXpr import XXpr
44+
45+
46+
class ARMSignedBitFieldExtractXData(ARMOpcodeXData):
47+
48+
def __init__(self, xdata: InstrXData) -> None:
49+
ARMOpcodeXData.__init__(self, xdata)
50+
51+
@property
52+
def vrd(self) -> "XVariable":
53+
return self.var(0, "vrd")
54+
55+
@property
56+
def xrn(self) -> "XXpr":
57+
return self.xpr(0, "xrn")
58+
59+
@property
60+
def xxrn(self) -> "XXpr":
61+
return self.xpr(1, "xxrn")
62+
63+
@property
64+
def result_simplified(self) -> str:
65+
return simplify_result(
66+
self.xdata.args[1], self.xdata.args[2], self.xrn, self.xxrn)
67+
68+
@property
69+
def annotation(self) -> str:
70+
assignment = str(self.vrd) + " := " + self.result_simplified
71+
return self.add_instruction_condition(assignment)
4272

4373

4474
@armregistry.register_tag("SBFX", ARMOpcode)
@@ -64,15 +94,8 @@ def operands(self) -> List[ARMOperand]:
6494
return [self.armd.arm_operand(i) for i in self.args]
6595

6696
def annotation(self, xdata: InstrXData) -> str:
67-
"""xdata format: a:vxx .
68-
69-
vars[0]: lhs
70-
xprs[0]: rhs1
71-
xprs[1]: value to be stored (syntactic)
72-
"""
73-
74-
lhs = str(xdata.vars[0])
75-
result = xdata.xprs[0]
76-
rresult = xdata.xprs[1]
77-
xresult = simplify_result(xdata.args[1], xdata.args[2], result, rresult)
78-
return lhs + " := " + xresult
97+
xd = ARMSignedBitFieldExtractXData(xdata)
98+
if xd.is_ok:
99+
return xd.annotation
100+
else:
101+
return "Error value"

‎chb/arm/opcodes/ARMSignedExtendHalfword.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,9 @@ def annotation(self, xdata: InstrXData) -> str:
7777
xprs[1]: rhs (simplified)
7878
"""
7979

80+
'''
8081
lhs = str(xdata.vars[0])
8182
result = str(xdata.xprs[1])
8283
return lhs + " := " + result
84+
'''
85+
return "pending"

‎chb/arm/opcodes/ARMUnsignedExtendAddByte.py‎

Lines changed: 41 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# ------------------------------------------------------------------------------
55
# The MIT License (MIT)
66
#
7-
# Copyright (c) 2021 Aarno Labs LLC
7+
# Copyright (c) 2021-2025 Aarno Labs LLC
88
#
99
# Permission is hereby granted, free of charge, to any person obtaining a copy
1010
# of this software and associated documentation files (the "Software"), to deal
@@ -30,7 +30,7 @@
3030
from chb.app.InstrXData import InstrXData
3131

3232
from chb.arm.ARMDictionaryRecord import armregistry
33-
from chb.arm.ARMOpcode import ARMOpcode, simplify_result
33+
from chb.arm.ARMOpcode import ARMOpcode, ARMOpcodeXData, simplify_result
3434
from chb.arm.ARMOperand import ARMOperand
3535

3636
import chb.util.fileutil as UF
@@ -39,6 +39,43 @@
3939

4040
if TYPE_CHECKING:
4141
from chb.arm.ARMDictionary import ARMDictionary
42+
from chb.invariants.XVariable import XVariable
43+
from chb.invariants.XXpr import XprCompound, XprConstant, XXpr
44+
45+
46+
class ARMUnsignedExtendAddByteXData(ARMOpcodeXData):
47+
"""
48+
Data format:
49+
- variables:
50+
0: vrd
51+
52+
- expressions:
53+
0: xrn
54+
1: xrm
55+
"""
56+
57+
def __init__(self, xdata: InstrXData) -> None:
58+
ARMOpcodeXData.__init__(self, xdata)
59+
60+
@property
61+
def vrd(self) -> "XVariable":
62+
return self.var(0, "vrd")
63+
64+
@property
65+
def xrn(self) -> "XXpr":
66+
return self.xpr(0, "xrn")
67+
68+
@property
69+
def xrm(self) -> "XXpr":
70+
return self.xpr(1, "xrm")
71+
72+
@property
73+
def annotation(self) -> str:
74+
lhs = str(self.vrd)
75+
rhs1 = str(self.xrn)
76+
rhs2 = str(self.xrm)
77+
assign = lhs + " := extend_add_byte(" + rhs1 + ", " + rhs2 + ")"
78+
return self.add_instruction_condition(assign)
4279

4380

4481
@armregistry.register_tag("UXTAB", ARMOpcode)
@@ -65,14 +102,5 @@ def operands(self) -> List[ARMOperand]:
65102
return [self.armd.arm_operand(self.args[i]) for i in [0, 1, 2]]
66103

67104
def annotation(self, xdata: InstrXData) -> str:
68-
"""xdata format a:vxx .
69-
70-
vars[0]: lhs
71-
xprs[0]: rhs1
72-
xprs[1]: rhs2
73-
"""
74-
75-
lhs = str(xdata.vars[0])
76-
op1 = str(xdata.xprs[0])
77-
op2 = str(xdata.xprs[1])
78-
return lhs + ":= extend_add_byte(" + op1 + ", " + op2 + ")"
105+
xd = ARMUnsignedExtendAddByteXData(xdata)
106+
return xd.annotation

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