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ARM:STM: update for conversion to C expressions
1 parent f73eb39 commit d1e0683

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1 file changed

+25
-14
lines changed

1 file changed

+25
-14
lines changed

chb/arm/opcodes/ARMStoreMultipleIncrementAfter.py

Lines changed: 25 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,10 @@ def cmemlhss(self) -> List["XVariable"]:
171171
def are_cmemlhss_ok(self) -> bool:
172172
return all(self.is_cvar_ok(i) for i in self.cmemlhs_range)
173173

174+
@property
175+
def baserhs(self) -> "XXpr":
176+
return self.xpr(0, "baserhs")
177+
174178
@property
175179
def rhs_range(self) -> Iterable[int]:
176180
return range(1, self.regcount + 1)
@@ -497,22 +501,32 @@ def ast_prov(
497501
return self.ast_prov_ldmstmcopy(astree, iaddr, bytestring, xdata)
498502

499503
xd = ARMStoreMultipleIncrementAfterXData(xdata)
500-
if not xd.is_ok:
504+
505+
if xd.are_cmemlhss_ok:
506+
memlhss = xd.cmemlhss
507+
elif xd.are_memlhss_ok:
508+
memlhss = xd.memlhss
509+
else:
501510
chklogger.logger.error(
502-
"STM: Error value encountered at address %s", iaddr)
511+
"STM: Error value encountered in LHSs at address %s", iaddr)
512+
return ([], [])
513+
514+
if xd.are_crhss_ok:
515+
regrhss = xd.crhss
516+
elif xd.are_rrhss_ok:
517+
regrhss = xd.rhss
518+
else:
519+
chklogger.logger.error(
520+
"STM: Error value encountered in RHSs at address %s", iaddr)
503521
return ([], [])
504522

505523
annotations: List[str] = [iaddr, "STM"]
506524

507-
'''
508-
baselhs = xdata.vars[0]
509-
baserhs = xdata.xprs[0]
510-
baseresult = xdata.xprs[1]
511-
baseresultr = xdata.xprs[2]
525+
baselhs = xd.baselhs
526+
baserhs = xd.baserhs
512527
baserdef = xdata.reachingdefs[0]
513528
baseuses = xdata.defuses[0]
514529
baseuseshigh = xdata.defuseshigh[0]
515-
'''
516530

517531
# low-level assignments
518532

@@ -522,8 +536,6 @@ def ast_prov(
522536
(baselval, _, _) = self.opargs[0].ast_lvalue(astree)
523537
(baserval, _, _) = self.opargs[0].ast_rvalue(astree)
524538

525-
memlhss = xd.memlhss
526-
regrhss = xd.rhss
527539
regrdefs = xdata.reachingdefs[1:]
528540
memuses = xdata.defuses[1:]
529541
memuseshigh = xdata.defuseshigh[1:]
@@ -578,12 +590,11 @@ def ast_prov(
578590
memlhs.denotation).base.is_basevar)):
579591
astree.add_expose_instruction(hl_assign.instrid)
580592

581-
'''
582593
if self.writeback:
583594

584595
# low-level base assignment
585596

586-
baseincr = 4 * regcount
597+
baseincr = 4 * xd.regcount
587598
baseincr_c = astree.mk_integer_constant(baseincr)
588599

589600
ll_base_lhs = baselval
@@ -598,9 +609,10 @@ def ast_prov(
598609

599610
# high-level base assignment
600611

612+
baseresult = xd.get_base_update_xpr()
601613
hl_base_lhs = XU.xvariable_to_ast_lval(baselhs, xdata, iaddr, astree)
602614
hl_base_rhs = XU.xxpr_to_ast_def_expr(
603-
baseresultr, xdata, iaddr, astree)
615+
baseresult, xdata, iaddr, astree)
604616
hl_base_assign = astree.mk_assign(
605617
hl_base_lhs,
606618
hl_base_rhs,
@@ -616,6 +628,5 @@ def ast_prov(
616628
astree.add_expr_reachingdefs(ll_base_rhs, [baserdef])
617629
astree.add_lval_defuses(hl_base_lhs, baseuses)
618630
astree.add_lval_defuses_high(hl_base_lhs, baseuseshigh)
619-
'''
620631

621632
return (hl_instrs, ll_instrs)

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