ARM: add base-updates to memory instructions

Author: sipma

chb/app/CHVersion.py

@@ -1 +1 @@
-chbversion: str = "0.3.0-20250908"
+chbversion: str = "0.3.0-20251011"

chb/app/InstrXData.py

@@ -578,6 +578,12 @@ def get_base_update_xpr(self) -> XXpr:
                 "Unexpected error value in base-update expression")
         return self.xprdictionary.xpr(xbuval)
 
+    def is_base_update_xpr_ok(self) -> bool:
+        xbutag = next(t for t in self.tags if t.startswith("xbu:"))
+        xix = int(xbutag[4:])
+        xbuval = self.args[xix]
+        return (xbuval != -2)
+
     def get_base_update_cxpr(self) -> XXpr:
         cbutag = next(t for t in self.tags if t.startswith("cbu:"))
         cix = int(cbutag[4:])

chb/arm/ARMAssembly.py

@@ -62,7 +62,7 @@ def opcode(self) -> ARMOpcode:
 
     @property
     def mnemonic(self) -> str:
-        return self.opcode.mnemonic
+        return self.opcode.mnemonic_stem
 
     def mnemonic_extension(self) -> str:
         return self.opcode.mnemonic_extension()

chb/arm/ARMOpcode.py

@@ -229,6 +229,9 @@ def get_base_update_xpr(self) -> "XXpr":
             raise UF.CHBError(
                 self.__class__.__name__ + " does not have writeback")
 
+    def is_base_update_xpr_ok(self) -> bool:
+        return self.xdata.is_base_update_xpr_ok()
+
     def get_base_update_cxpr(self) -> "XXpr":
         if self.is_writeback:
             return self.xdata.get_base_update_cxpr()
@@ -239,7 +242,10 @@ def get_base_update_cxpr(self) -> "XXpr":
     def writeback_update(self) -> str:
         if self.xdata.has_base_update():
             vbu = self.get_base_update_var()
-            xbu = self.get_base_update_cxpr()
+            if self.is_base_update_xpr_ok():
+                xbu = str(self.get_base_update_cxpr())
+            else:
+                xbu = "?"
             return "; wbu: " + str(vbu) + " := " + str(xbu)
         else:
             return ""

chb/arm/opcodes/ARMBitwiseBitClear.py

@@ -156,6 +156,15 @@ def operands(self) -> List[ARMOperand]:
     def opargs(self) -> List[ARMOperand]:
         return [self.armd.arm_operand(i) for i in self.args[1: -1]]
 
+    def mnemonic_extension(self) -> str:
+        cc = ARMOpcode.mnemonic_extension(self)
+        wb = "S" if self.is_writeback else ""
+        return wb + cc
+
+    @property
+    def is_writeback(self) -> bool:
+        return self.args[0] == 1
+
     def annotation(self, xdata: InstrXData) -> str:
         xd = ARMBitwiseBitClearXData(xdata)
         return xd.annotation

chb/arm/opcodes/ARMLoadCoprocessor.py

@@ -41,6 +41,8 @@
     from chb.arm.ARMDictionary import ARMDictionary
 
 
+@armregistry.register_tag("LDC2", ARMOpcode)
+@armregistry.register_tag("LDC2L", ARMOpcode)
 @armregistry.register_tag("LDCL", ARMOpcode)
 @armregistry.register_tag("LDC", ARMOpcode)
 class ARMLoadCoprocessor(ARMOpcode):

chb/arm/opcodes/ARMLoadRegisterByte.py

@@ -198,6 +198,10 @@ def operands(self) -> List[ARMOperand]:
     def opargs(self) -> List[ARMOperand]:
         return [self.armd.arm_operand(self.args[i]) for i in [0, 1, 2, 3]]
 
+    @property
+    def is_write_back(self) -> bool:
+        return self.opargs[3].is_write_back
+
     def lhs(self, xdata: InstrXData) -> List[XVariable]:
         xd = ARMLoadRegisterByteXData(xdata)
         return [xd.vrt]
@@ -324,6 +328,11 @@ def has_cast() -> bool:
                 annotations=annotations)
             ll_assigns: List[AST.ASTInstruction] = [ll_assign, ll_addr_assign]
 
+            if not xd.is_base_update_xpr_ok():
+                chklogger.logger.error(
+                    "LDRB: Error encountered for writeback address at address %s", iaddr)
+                return ([], ll_assigns)
+
             basereg = xd.get_base_update_var()
             newaddr = xd.get_base_update_xpr()
             hl_addr_lhs = XU.xvariable_to_ast_lval(basereg, xdata, iaddr, astree)

chb/arm/opcodes/ARMLoadRegisterHalfword.py

@@ -193,6 +193,10 @@ def operands(self) -> List[ARMOperand]:
     def opargs(self) -> List[ARMOperand]:
         return [self.armd.arm_operand(self.args[i]) for i in [0, 1, 2, 3]]
 
+    @property
+    def is_write_back(self) -> bool:
+        return self.opargs[3].is_write_back
+
     def lhs(self, xdata: InstrXData) -> List[XVariable]:
         xd = ARMLoadRegisterHalfwordXData(xdata)
         return [xd.vrt]

chb/arm/opcodes/ARMLoadRegisterSignedByte.py

@@ -195,10 +195,6 @@ def ast_prov(
         defuses = xdata.defuses
         defuseshigh = xdata.defuseshigh
 
-        hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
-        hl_rhs = XU.xxpr_to_ast_def_expr(
-            rhs, xdata, iaddr, astree, size=1, memaddr=xaddr)
-
         hl_assign = astree.mk_assign(
             hl_lhs,
             hl_rhs,

chb/arm/opcodes/ARMMove.py

@@ -340,6 +340,7 @@ def ast_prov_predicate_assign(
             chklogger.logger.warning(
                 "Predicate assignment without associated predicate at "
                 + "address %s", iaddr)
+            astree.add_instr_address(ll_assign, [iaddr])
             return ([], [ll_assign])
 
         rhs = xd.cpredicate if xd.is_cpredicate_ok else xd.xpredicate