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ARM:relax astprov condition
1 parent 72d1e66 commit fb33541

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2 files changed

+2
-2
lines changed

2 files changed

+2
-2
lines changed

chb/arm/opcodes/ARMStoreRegister.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,7 @@ def ast_prov(
265265
hl_lhs = XU.xvariable_to_ast_lval(
266266
lhsvar, xdata, iaddr, astree, memaddr=memaddr)
267267

268-
elif xd.is_vmem_unknown and xd.is_address_known:
268+
elif xd.is_address_known:
269269
memaddr = xd.xaddr
270270
hl_lhs = XU.xmemory_dereference_lval(memaddr, xdata, iaddr, astree)
271271

chb/arm/opcodes/ARMStoreRegisterByte.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ def ast_prov(
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hl_lhs = XU.xvariable_to_ast_lval(
212212
lhsvar, xdata, iaddr, astree, memaddr=memaddr)
213213

214-
elif xd.is_vmem_unknown and xd.is_address_known:
214+
elif xd.is_address_known:
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memaddr = xd.xaddr
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hl_lhs = XU.xmemory_dereference_lval(memaddr, xdata, iaddr, astree)
217217

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