CHB:ARM:add disassembly support for FLDMIAX (arm)

Author: sipma

CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml

@@ -1703,6 +1703,18 @@ let parse_misc_6_type (instr: doubleword_int) (cond: int) =
      (* VMOV<c> <Dm>, <Rt>, <Rt2> *)
      VectorMoveDDS (c, VfpNone, rt WR, rt2 WR, rtd WR, dm RD)
 
+  (* FLDMIAX{<c>}{<q>}>Rn>{!},<dreglist> *)
+  (* <cc><6>01001DW1<rn><vd>1011<-imm7>1 *)
+  | (1, 1, 11) when (bv 22) = 0 && (bv 0) = 1 ->
+     let d = prefix_bit (bv 22) (b 15 12) in
+     let rnreg = get_arm_reg (b 19 16) in
+     let rn = arm_register_op rnreg in
+     let regs = (b 7 1) in
+     let rl = arm_extension_register_list_op XDouble d regs in
+     let mem = mk_arm_mem_multiple_op ~size:8 rnreg regs in
+     (* FLXMIAX<c>, <list> *)
+     FLoadMultipleIncrementAfter (false, c, rn RD, rl WR, mem RD)
+
   (* <cc><6>01D11<13><vd><10><-imm8-> *)   (* VPOP - A2 *)
   | (1, 3, 10) when (b 19 16) = 13 ->
      let d = postfix_bit (bv 22) (b 15 12) in

CodeHawk/CHT/CHB_tests/bchlibarm32_tests/txbchlibarm32/bCHDisassembleARMInstructionTest.ml

@@ -197,6 +197,10 @@ let arm_pc_relative () =
 
 let arm_vector () =
   let tests = [
+      ("FLDMIAX",                     "210b90ec",
+       "FLDMIAX        R0, {D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15}");
+      ("FSTMIAX",                     "210b80ec",
+       "FSTMIAX        R0, {D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15}");
       ("VDUP.32",                     "474cfcf3", "VDUP.32        Q10, D7[1]");
       ("VDUP.32-scalar",              "622cfcf3", "VDUP.32        Q9, D18[1]");
       ("VEOR-Q",                      "746106f3", "VEOR           Q3, Q3, Q10");