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steenlsteenl
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FSM cleanups
1 parent 3fb05be commit e69638c

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4 files changed

+28155
-31986
lines changed

4 files changed

+28155
-31986
lines changed

‎ualink_turbo64_v1_00_a/hdl/verilog/ualink_turbo64.v‎

Lines changed: 71 additions & 131 deletions
Original file line numberDiff line numberDiff line change
@@ -108,35 +108,15 @@ module ualink_turbo64
108108

109109
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES);
110110

111-
parameter NUM_STATES = 24;
111+
parameter NUM_STATES = 7;
112112
parameter IDLE = 0;
113113
parameter PKT_PROC = 1;
114-
parameter READ_OPc1 = 2;
115-
parameter READ_OPc2 = 3;
116-
parameter READ_OPc3 = 4;
117-
parameter READ_OPc4 = 5;
118-
parameter READ_OPc5 = 6;
119-
parameter READ_OPc6 = 7;
120-
parameter READ_OPc7 = 8;
121-
parameter READ_OPc8 = 9;
122-
parameter READ_OPc9 = 20;
123-
parameter READ_OPca = 21;
124-
parameter READ_OPcb = 22;
125-
126-
parameter WRITE_OPc0 = 10;
127-
parameter WRITE_OPc1 = 11;
128-
parameter WRITE_OPc2 = 12;
129-
parameter WRITE_OPc3 = 13;
130-
parameter WRITE_OPc4 = 14;
131-
parameter WRITE_OPc5 = 15;
132-
parameter WRITE_OPc6 = 16;
133-
parameter WRITE_OPc7 = 17;
134-
parameter WRITE_OPc8 = 18;
135-
parameter WRITE_OPc9 = 19;
136-
137-
parameter START_MAC = 22;
138-
parameter KV_SET = 23;
139-
parameter KV_GET = 24;
114+
parameter READ_OP =2;
115+
116+
parameter WRITE_OP =3;
117+
parameter START_MAC = 4;
118+
parameter KV_SET = 5;
119+
parameter KV_GET = 6;
140120

141121
localparam MAX_PKT_SIZE = 2000; // In bytes
142122
localparam IN_FIFO_DEPTH_BIT = log2(MAX_PKT_SIZE/(C_M_AXIS_DATA_WIDTH / 8));
@@ -164,6 +144,8 @@ module ualink_turbo64
164144

165145
reg [NUM_STATES-1:0] state, state_next;
166146
reg MAC_start, MAC_start_next;
147+
reg [3:0] write_cnt = 4'h0, write_cnt_next = 4'h0; // needs to count to 9 (0–8)
148+
reg [3:0] read_cnt = 4'h0, read_cnt_next = 4'h0; // needs to count to 11 (0–10)
167149
reg [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata_reg = "01234567"; //register to hold read response data
168150
reg [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata_reg_next = "01234567"; //register to hold read response data
169151
reg [C_M_AXIS_DATA_WIDTH - 1:0] frame_h0d1_reg = "00000000000000000000000000000000"; //register to hold read response data
@@ -352,10 +334,10 @@ mac_16x8_inst
352334
//decode command
353335
if ((frame_h0d4_reg[63:48]) == 16'h0245) begin //write operation
354336
we_a_next = 0;
355-
state_next = WRITE_OPc0;
337+
state_next = WRITE_OP;
356338
end
357339
else if ((frame_h0d4_reg[63:48]) == 16'h0145) begin //read to addr 1
358-
state_next = READ_OPc1; // states 2,3,4,5,6,7,8,9
340+
state_next = READ_OP; // states 2,3,4,5,6,7,8,9
359341
we_a_next = 0;
360342
end //if
361343
else if ((frame_h0d4_reg[63:48]) == 16'h0345) begin //Kickstart MAC
@@ -388,109 +370,63 @@ mac_16x8_inst
388370
state_next = PKT_PROC;
389371
MAC_start_next = 0;
390372
end
391-
WRITE_OPc0: begin //grab address from Header 5
392-
state_next = WRITE_OPc1;
393-
addr_a_next = s_axis_tdata_0[63:56]; //frame_h0d3_reg[63:56]; //8'b00; //dummy addr
394-
we_a_next = 1;
395-
din_a = dmark;
396-
end
397-
WRITE_OPc1: begin // this cycle writes 1st word and preps for next
398-
state_next = WRITE_OPc2;
399-
addr_a_next = addr_a + 1;
400-
din_a = s_axis_tdata_0;
401-
end
402-
WRITE_OPc2: begin //D0
403-
state_next = WRITE_OPc3;
404-
addr_a_next = addr_a + 1;
405-
din_a = s_axis_tdata_0;
406-
end
407-
WRITE_OPc3: begin
408-
state_next = WRITE_OPc4;
409-
addr_a_next = addr_a + 1;
410-
din_a = s_axis_tdata_0;
411-
end
412-
WRITE_OPc4: begin
413-
state_next = WRITE_OPc5;
414-
addr_a_next = addr_a + 1;
415-
din_a = s_axis_tdata_0;
416-
end
417-
WRITE_OPc5: begin
418-
state_next = WRITE_OPc6;
419-
addr_a_next = addr_a + 1;
420-
din_a = s_axis_tdata_0;
421-
end
422-
WRITE_OPc6: begin
423-
state_next = WRITE_OPc7;
424-
addr_a_next = addr_a + 1;
425-
din_a = s_axis_tdata_0;
426-
end
427-
WRITE_OPc7: begin
428-
state_next = WRITE_OPc8;
429-
addr_a_next = addr_a + 1;
430-
din_a = s_axis_tdata_0;
431-
end
432-
WRITE_OPc8: begin //prepare for final word.
433-
state_next = PKT_PROC;
434-
addr_a_next = addr_a + 1;
435-
din_a = s_axis_tdata_0;
436-
we_a_next = 0;
437-
end
438373

439-
READ_OPc1: begin //first 8B
440-
state_next = READ_OPc2;
441-
addr_a_next = addr_a + 1;
442-
addr_a_next = s_axis_tdata_0[63:56]; //frame_h0d2_reg[63:56]; // 8'h0; //replace with parsed addr
443-
m_axis_tdata_reg_next = dout_a;
444-
end
445-
READ_OPc2: begin // 8B
446-
state_next = READ_OPc3;
447-
addr_a_next = addr_a + 1;
448-
m_axis_tdata_reg_next = dout_a;
449-
end
450-
READ_OPc3: begin // 8B
451-
state_next = READ_OPc4;
452-
addr_a_next = addr_a + 1;
453-
m_axis_tdata_reg_next = dout_a;
454-
end
455-
READ_OPc4: begin // 8B
456-
state_next = READ_OPc5;
457-
addr_a_next = addr_a + 1;
458-
m_axis_tdata_reg_next = dout_a;
459-
end
460-
READ_OPc5: begin // 8B
461-
state_next = READ_OPc6;
462-
addr_a_next = addr_a + 1;
463-
m_axis_tdata_reg_next = dout_a;
464-
end
465-
READ_OPc6: begin //first 8B
466-
state_next = READ_OPc7;
467-
addr_a_next = addr_a + 1;
468-
m_axis_tdata_reg_next = dout_a;
469-
end
470-
READ_OPc7: begin //first 8B
471-
state_next = READ_OPc8;
472-
addr_a_next = addr_a + 1;
473-
m_axis_tdata_reg_next = dout_a;
474-
end
475-
READ_OPc8: begin //first 8B
476-
state_next = READ_OPc9;
477-
addr_a_next = addr_a + 1;
478-
m_axis_tdata_reg_next = dout_a;
479-
end
480-
READ_OPc9: begin //first 8B
481-
state_next = READ_OPca;
482-
addr_a_next = addr_a + 1;
483-
m_axis_tdata_reg_next = dout_a;
484-
end
485-
READ_OPca: begin //first 8B
486-
state_next = READ_OPcb;
487-
addr_a_next = addr_a + 1;
488-
m_axis_tdata_reg_next = dout_a;
374+
WRITE_OP: begin
375+
// defaults
376+
state_next = WRITE_OP;
377+
addr_a_next = addr_a;
378+
we_a_next = 1;
379+
din_a = s_axis_tdata_0;
380+
write_cnt_next = write_cnt;
381+
382+
if (write_cnt == 0) begin
383+
// first cycle: grab address + write marker
384+
addr_a_next = s_axis_tdata_0[63:56];
385+
din_a = dmark;
386+
write_cnt_next = write_cnt + 1;
387+
end
388+
else if (write_cnt < 8) begin
389+
// middle data words
390+
addr_a_next = addr_a + 1;
391+
din_a = s_axis_tdata_0;
392+
write_cnt_next = write_cnt + 1;
393+
end
394+
else begin
395+
// final word
396+
addr_a_next = addr_a + 1;
397+
din_a = s_axis_tdata_0;
398+
we_a_next = 0;
399+
write_cnt_next = 0;
400+
state_next = PKT_PROC;
401+
end
489402
end
490-
READ_OPcb: begin //first 8B
491-
state_next = PKT_PROC;
492-
addr_a_next = addr_a + 1;
493-
m_axis_tdata_reg_next = dout_a;
403+
404+
READ_OP: begin
405+
// defaults
406+
state_next = READ_OP;
407+
addr_a_next = addr_a;
408+
m_axis_tdata_reg_next = m_axis_tdata_reg;
409+
read_cnt_next = read_cnt;
410+
411+
if (read_cnt == 0) begin
412+
// first cycle: load base address
413+
addr_a_next = s_axis_tdata_0[63:56];
414+
m_axis_tdata_reg_next = dout_a;
415+
read_cnt_next = read_cnt + 1;
416+
end
417+
else if (read_cnt < 10) begin
418+
// middle reads
419+
addr_a_next = addr_a + 1;
420+
m_axis_tdata_reg_next = dout_a;
421+
read_cnt_next = read_cnt + 1;
422+
end
423+
else begin
424+
// final read
425+
addr_a_next = addr_a + 1;
426+
m_axis_tdata_reg_next = dout_a;
427+
read_cnt_next = 0;
428+
state_next = PKT_PROC;
429+
end
494430
end
495431

496432
endcase // case(state)
@@ -500,7 +436,8 @@ mac_16x8_inst
500436
if(~axi_resetn) begin
501437
state <= IDLE;
502438
cur_queue <= 0;
503-
// din_a <= 0;
439+
write_cnt <= 0;
440+
read_cnt <= 0;
504441
we_a <= 0;
505442
end
506443
else begin
@@ -513,6 +450,9 @@ mac_16x8_inst
513450
frame_h0d4_reg <= frame_h0d3_reg;
514451
frame_h0d3_reg <= frame_h0d2_reg;
515452
frame_h0d2_reg <= frame_h0d1_reg;
453+
write_cnt <= write_cnt_next;
454+
read_cnt <= read_cnt_next;
455+
516456
end
517457
end
518458

‎ualink_turbo64_v1_00_a/hdl/verilog/ualink_turbo64_tb.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ For now all is AXI_0, we leave artifacts of port interfaces 0-4 for future multi
1616
to run in Icarus simulator use:
1717
iverilog -o ualink_turbo64_tb.vvp .\ualink_turbo64_tb.v ualink_turbo64.v .\fallthrough_small_fifo_v2.v .\small_fifo_v3.v .\ualink_dpmem.v
1818
vvp ualink_turbo64_tb.vvp
19-
gtkwave.exe .\ualink_turbo_tb.vcd
19+
gtkwave.exe .\ualink_turbo64_tb.vcd
2020
2121
2222
*

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