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Ok(w.write_all(&b)?) -> w.write_all(&b)
1 parent 3bac661 commit 4b8eb26

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25 files changed

+100
-100
lines changed

25 files changed

+100
-100
lines changed

lib/xdrgen/generators/rust/src/types.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -667,7 +667,7 @@ impl WriteXdr for i32 {
667667
let b: [u8; 4] = self.to_be_bytes();
668668
w.with_limited_depth(|w| {
669669
w.consume_len(b.len())?;
670-
Ok(w.write_all(&b)?)
670+
w.write_all(&b)
671671
})
672672
}
673673
}
@@ -690,7 +690,7 @@ impl WriteXdr for u32 {
690690
let b: [u8; 4] = self.to_be_bytes();
691691
w.with_limited_depth(|w| {
692692
w.consume_len(b.len())?;
693-
Ok(w.write_all(&b)?)
693+
w.write_all(&b)
694694
})
695695
}
696696
}
@@ -713,7 +713,7 @@ impl WriteXdr for i64 {
713713
let b: [u8; 8] = self.to_be_bytes();
714714
w.with_limited_depth(|w| {
715715
w.consume_len(b.len())?;
716-
Ok(w.write_all(&b)?)
716+
w.write_all(&b)
717717
})
718718
}
719719
}
@@ -736,7 +736,7 @@ impl WriteXdr for u64 {
736736
let b: [u8; 8] = self.to_be_bytes();
737737
w.with_limited_depth(|w| {
738738
w.consume_len(b.len())?;
739-
Ok(w.write_all(&b)?)
739+
w.write_all(&b)
740740
})
741741
}
742742
}

spec/output/generator_spec_rust/block_comments.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/const.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/enum.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/nesting.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/optional.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/struct.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/test.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust/union.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

spec/output/generator_spec_rust_custom_jsonschema_impls/block_comments.x/MyXDR.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ impl WriteXdr for i32 {
677677
let b: [u8; 4] = self.to_be_bytes();
678678
w.with_limited_depth(|w| {
679679
w.consume_len(b.len())?;
680-
Ok(w.write_all(&b)?)
680+
w.write_all(&b)
681681
})
682682
}
683683
}
@@ -700,7 +700,7 @@ impl WriteXdr for u32 {
700700
let b: [u8; 4] = self.to_be_bytes();
701701
w.with_limited_depth(|w| {
702702
w.consume_len(b.len())?;
703-
Ok(w.write_all(&b)?)
703+
w.write_all(&b)
704704
})
705705
}
706706
}
@@ -723,7 +723,7 @@ impl WriteXdr for i64 {
723723
let b: [u8; 8] = self.to_be_bytes();
724724
w.with_limited_depth(|w| {
725725
w.consume_len(b.len())?;
726-
Ok(w.write_all(&b)?)
726+
w.write_all(&b)
727727
})
728728
}
729729
}
@@ -746,7 +746,7 @@ impl WriteXdr for u64 {
746746
let b: [u8; 8] = self.to_be_bytes();
747747
w.with_limited_depth(|w| {
748748
w.consume_len(b.len())?;
749-
Ok(w.write_all(&b)?)
749+
w.write_all(&b)
750750
})
751751
}
752752
}

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