Set clock range

Author: dtjones190

README.md

@@ -32,6 +32,7 @@ In `src/main.rs` add:
 ```rust
 use stm32_eth::{
     hal::gpio::GpioExt,
+    hal::rcc::RccExt,
     stm32::Peripherals,
 };
 
@@ -54,10 +55,12 @@ fn main() {
     // Allocate the ring buffers
     let mut rx_ring: [RingEntry<_>; 8] = Default::default();
     let mut tx_ring: [RingEntry<_>; 2] = Default::default();
+    let clocks = p.RCC.constrain().cfgr.freeze();
     // Instantiate driver
     let mut eth = Eth::new(
         p.ETHERNET_MAC, p.ETHERNET_DMA,
-        &mut rx_ring[..], &mut tx_ring[..]
+        &mut rx_ring[..], &mut tx_ring[..],
+        &clocks
     );
     // If you have a handler, enable interrupts
     eth.enable_interrupt(&mut cp.NVIC);

examples/ip.rs

@@ -8,6 +8,7 @@ use cortex_m_rt::{entry, exception};
 use stm32_eth::{
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
     hal::gpio::GpioExt,
+    hal::rcc::RccExt,
 };
 
 use core::cell::RefCell;
@@ -74,11 +75,13 @@ fn main() -> ! {
 
     let mut rx_ring: [RingEntry<_>; 8] = Default::default();
     let mut tx_ring: [RingEntry<_>; 2] = Default::default();
+    let clocks = p.RCC.constrain().cfgr.freeze();
     let mut eth = Eth::new(
         p.ETHERNET_MAC,
         p.ETHERNET_DMA,
         &mut rx_ring[..],
         &mut tx_ring[..],
+        &clocks,
     );
     eth.enable_interrupt();
 

examples/pktgen.rs

@@ -12,6 +12,7 @@ use cortex_m::interrupt::Mutex;
 use stm32_eth::{
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
     hal::gpio::GpioExt,
+    hal::rcc::RccExt,
 };
 
 use core::fmt::Write;
@@ -48,11 +49,13 @@ fn main() -> ! {
 
     let mut rx_ring: [RingEntry<_>; 16] = Default::default();
     let mut tx_ring: [RingEntry<_>; 8] = Default::default();
+    let clocks = p.RCC.constrain().cfgr.freeze();
     let mut eth = Eth::new(
         p.ETHERNET_MAC,
         p.ETHERNET_DMA,
         &mut rx_ring[..],
         &mut tx_ring[..],
+        &clocks,
     );
     eth.enable_interrupt();
 

src/lib.rs

@@ -15,6 +15,10 @@ pub use stm32f4xx_hal as hal;
 pub use stm32f4xx_hal::stm32;
 
 use stm32::{Interrupt, ETHERNET_DMA, ETHERNET_MAC, NVIC};
+use hal::{
+        rcc::Clocks,
+        time::U32Ext,
+};
 
 use cortex_m::asm;
 
@@ -46,21 +50,6 @@ const PHY_ADDR: u8 = 0;
 /// From the datasheet: *VLAN Frame maxsize = 1522*
 const MTU: usize = 1522;
 
-#[allow(dead_code)]
-mod consts {
-    /* For HCLK 60-100 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_42: u8 = 0;
-    /* For HCLK 100-150 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_62: u8 = 1;
-    /* For HCLK 20-35 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_16: u8 = 2;
-    /* For HCLK 35-60 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_26: u8 = 3;
-    /* For HCLK 150-168 MHz */
-    pub const ETH_MACMIIAR_CR_HCLK_DIV_102: u8 = 4;
-}
-use self::consts::*;
-
 /// Ethernet driver for *STM32* chips with a *LAN8742*
 /// [`Phy`](phy/struct.Phy.html) like they're found on STM Nucleo-144
 /// boards.
@@ -89,24 +78,48 @@ impl<'rx, 'tx> Eth<'rx, 'tx> {
         eth_dma: ETHERNET_DMA,
         rx_buffer: &'rx mut [RxRingEntry],
         tx_buffer: &'tx mut [TxRingEntry],
+        clocks: &Clocks,
     ) -> Self {
         let mut eth = Eth {
             eth_mac,
             eth_dma,
             rx_ring: RxRing::new(rx_buffer),
             tx_ring: TxRing::new(tx_buffer),
         };
-        eth.init();
+        eth.init(clocks);
         eth.rx_ring.start(&eth.eth_dma);
         eth.tx_ring.start(&eth.eth_dma);
         eth
     }
 
-    fn init(&mut self) -> &Self {
+    fn init(&mut self, clocks : &Clocks) -> &Self {
         self.reset_dma_and_wait();
 
+        /* For HCLK 60-100 MHz */
+        const ETH_MACMIIAR_CR_HCLK_DIV_42: u8 = 0;
+        /* For HCLK 100-150 MHz */
+        const ETH_MACMIIAR_CR_HCLK_DIV_62: u8 = 1;
+        /* For HCLK 20-35 MHz */
+        const ETH_MACMIIAR_CR_HCLK_DIV_16: u8 = 2;
+        /* For HCLK 35-60 MHz */
+        const ETH_MACMIIAR_CR_HCLK_DIV_26: u8 = 3;
+        /* For HCLK 150+ MHz */
+        const ETH_MACMIIAR_CR_HCLK_DIV_102: u8 = 4;
+
         // set clock range in MAC MII address register
-        let clock_range = ETH_MACMIIAR_CR_HCLK_DIV_26;
+        let clock_range;
+        if clocks.hclk() <= 35.mhz().into() {
+            clock_range = ETH_MACMIIAR_CR_HCLK_DIV_16;
+        } else if clocks.hclk() <= 60.mhz().into() {
+            clock_range = ETH_MACMIIAR_CR_HCLK_DIV_26;
+        } else if clocks.hclk() <= 100.mhz().into() {
+            clock_range = ETH_MACMIIAR_CR_HCLK_DIV_42;
+        } else if clocks.hclk() <= 150.mhz().into() {
+            clock_range = ETH_MACMIIAR_CR_HCLK_DIV_62;
+        } else {
+            clock_range = ETH_MACMIIAR_CR_HCLK_DIV_102;
+        }
+
         self.eth_mac
             .macmiiar
             .modify(|_, w| unsafe { w.cr().bits(clock_range) });