Fix startup order of pins, DMA and MAC

Make `new` functions pub(crate)

Author: Johannes Draaijer

src/dma.rs

@@ -4,7 +4,7 @@ use crate::{
     rx::{RxPacket, RxRing},
     stm32::{Interrupt, ETHERNET_DMA},
     tx::TxRing,
-    EthernetMAC, RxError, RxRingEntry, TxError, TxRingEntry,
+    RxError, RxRingEntry, TxError, TxRingEntry,
 };
 
 /// Ethernet DMA.
@@ -21,12 +21,7 @@ impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {
     /// - Make sure that the buffers reside in a memory region that is
     /// accessible by the peripheral. Core-Coupled Memory (CCM) is
     /// usually not accessible.
-    //
-    // NOTE: eth_mac is unused, but required for initialization as
-    // owning an [`EthernetMAC`] requires that all of it's checks
-    // (GPIO, clock speed) have passed.
-    pub fn new(
-        #[allow(unused)] eth_mac: &EthernetMAC,
+    pub(crate) fn new(
         eth_dma: ETHERNET_DMA,
         rx_buffer: &'rx mut [RxRingEntry],
         tx_buffer: &'tx mut [TxRingEntry],
@@ -166,6 +161,8 @@ impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {
 
 /// A summary of the reasons for the interrupt
 /// that occured
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Debug, Clone, Copy)]
 pub struct InterruptReasonSummary {
     pub is_rx: bool,
     pub is_tx: bool,

src/lib.rs

@@ -87,9 +87,11 @@ where
     RXD0: RmiiRxD0 + AlternateVeryHighSpeed,
     RXD1: RmiiRxD1 + AlternateVeryHighSpeed,
 {
-    let mac = EthernetMAC::new(eth_mac, eth_mmc, clocks, pins)?;
+    pins.setup_pins();
+    setup::setup();
 
-    let dma = EthernetDMA::new(&mac, eth_dma, rx_buffer, tx_buffer);
+    let dma = EthernetDMA::new(eth_dma, rx_buffer, tx_buffer);
+    let mac = EthernetMAC::new(eth_mac, eth_mmc, clocks)?;
 
     Ok((dma, mac))
 }
@@ -133,9 +135,11 @@ where
     MDIO: mac::MdioPin,
     MDC: mac::MdcPin,
 {
-    let mac = EthernetMAC::new(eth_mac, eth_mmc, clocks, pins)?.with_mii(mdio, mdc);
+    pins.setup_pins();
+    setup::setup();
 
-    let dma = EthernetDMA::new(&mac, eth_dma, rx_buffer, tx_buffer);
+    let dma = EthernetDMA::new(eth_dma, rx_buffer, tx_buffer);
+    let mac = EthernetMAC::new(eth_mac, eth_mmc, clocks)?.with_mii(mdio, mdc);
 
     Ok((dma, mac))
 }

src/mac/mod.rs

@@ -2,9 +2,7 @@ use core::ops::Deref;
 
 use crate::{
     hal::rcc::Clocks,
-    setup::*,
     stm32::{ETHERNET_MAC, ETHERNET_MMC},
-    EthPins,
 };
 
 mod miim;
@@ -45,25 +43,11 @@ impl EthernetMAC {
     ///
     /// Additionally, an optional `impl` of the [`ieee802_3_miim::Miim`] trait is available
     /// with the `ieee802_3_miim` feature (enabled by default), for PHY communication.
-    pub fn new<REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1>(
+    pub(crate) fn new(
         eth_mac: ETHERNET_MAC,
         eth_mmc: ETHERNET_MMC,
         clocks: Clocks,
-        pins: EthPins<REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1>,
-    ) -> Result<Self, WrongClock>
-    where
-        REFCLK: RmiiRefClk + AlternateVeryHighSpeed,
-        CRS: RmiiCrsDv + AlternateVeryHighSpeed,
-        TXEN: RmiiTxEN + AlternateVeryHighSpeed,
-        TXD0: RmiiTxD0 + AlternateVeryHighSpeed,
-        TXD1: RmiiTxD1 + AlternateVeryHighSpeed,
-        RXD0: RmiiRxD0 + AlternateVeryHighSpeed,
-        RXD1: RmiiRxD1 + AlternateVeryHighSpeed,
-    {
-        pins.setup_pins();
-
-        setup();
-
+    ) -> Result<Self, WrongClock> {
         let clock_frequency = clocks.hclk().to_Hz();
 
         let clock_range = match clock_frequency {