Initial H7 support

Author: datdenkikniet

Cargo.toml

@@ -25,11 +25,13 @@ stm32f7xx-hal = { version = "0.7.0", optional = true }
 stm32f4xx-hal = { version = "0.14", optional = true }
 stm32f4 = { version = "0.15", optional = true }
 stm32f1xx-hal = { version = "0.10", optional = true }
+stm32h7xx-hal = { version = "0.13", optional = true }
 ieee802_3_miim = "0.8"
 cortex-m = "0.7"
 log = { version = "0.4", optional = true }
 defmt = { version = "0.3", optional = true }
 siphasher = "*"
+paste = { version = "1.0", optional = true }
 
 [dependencies.smoltcp]
 version = "0.8.2"
@@ -41,6 +43,12 @@ default = [ "defmt", "ptp" ]
 device-selected = []
 fence = []
 ptp = [ ]
+f-series = [ ]
+
+stm32f1xx-hal = [ "dep:stm32f1xx-hal", "f-series" ]
+stm32f4xx-hal = [ "dep:stm32f4xx-hal", "f-series" ]
+stm32f7xx-hal = [ "dep:stm32f7xx-hal", "f-series" ]
+stm32h7xx-hal = [ "dep:stm32h7xx-hal", "paste"  ]
 
 stm32f107 = ["stm32f1xx-hal/stm32f107", "device-selected"]
 
@@ -63,6 +71,8 @@ stm32f777 = ["stm32f7xx-hal/stm32f777", "device-selected", "fence"]
 stm32f778 = ["stm32f7xx-hal/stm32f778", "device-selected", "fence"]
 stm32f779 = ["stm32f7xx-hal/stm32f779", "device-selected", "fence"]
 
+stm32h735 = ["stm32h7xx-hal/stm32h735", "device-selected", "fence"]
+
 smoltcp-phy = ["smoltcp"]
 
 [dev-dependencies]

build.rs

@@ -1,5 +1,4 @@
 fn main() {
-    #[cfg(feature = "stm32f1xx-hal")]
     println!("cargo:rustc-link-search=memory.x");
 
     let hse = std::env::var("STM32_ETH_EXAMPLE_HSE");

examples/arp.rs

@@ -17,11 +17,13 @@ use cortex_m_rt::{entry, exception};
 use cortex_m::interrupt::Mutex;
 use stm32_eth::{
     dma::{RxDescriptor, TxDescriptor},
-    mac::{phy::BarePhy, Phy},
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
     Parts, MTU,
 };
 
+#[cfg(feature = "f-series")]
+use stm32_eth::mac::{phy::BarePhy, Phy};
+
 pub mod common;
 
 use stm32_eth::dma::{RxDescriptorRing, TxDescriptorRing, TxError};
@@ -31,6 +33,17 @@ const PHY_ADDR: u8 = 0;
 static TIME: Mutex<RefCell<usize>> = Mutex::new(RefCell::new(0));
 static ETH_PENDING: Mutex<RefCell<bool>> = Mutex::new(RefCell::new(false));
 
+/// On H7s, the ethernet DMA does not have access to the normal ram
+/// so we must explicitly put them in SRAM.
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut TX_DESCRIPTORS: [TxDescriptor; 4] = [TxDescriptor::new(); 4];
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut TX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
+static mut RX_DESCRIPTORS: [RxDescriptor; 4] = [RxDescriptor::new(); 4];
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
+static mut RX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
+
 #[entry]
 fn main() -> ! {
     let p = Peripherals::take().unwrap();
@@ -44,13 +57,8 @@ fn main() -> ! {
 
     let (eth_pins, mdio, mdc, _) = common::setup_pins(gpio);
 
-    let mut rx_descriptors: [RxDescriptor; 2] = Default::default();
-    let mut rx_buffers: [[u8; MTU]; 2] = [[0u8; MTU]; 2];
-    let rx_ring = RxDescriptorRing::new(&mut rx_descriptors, &mut rx_buffers);
-
-    let mut tx_descriptors: [TxDescriptor; 2] = Default::default();
-    let mut tx_buffers: [[u8; MTU]; 2] = [[0u8; MTU]; 2];
-    let tx_ring = TxDescriptorRing::new(&mut tx_descriptors, &mut tx_buffers);
+    let rx_ring = RxDescriptorRing::new(unsafe { &mut RX_DESCRIPTORS }, unsafe { &mut RX_BUFFERS });
+    let tx_ring = TxDescriptorRing::new(unsafe { &mut TX_DESCRIPTORS }, unsafe { &mut TX_BUFFERS });
 
     let Parts {
         mut dma,
@@ -62,11 +70,16 @@ fn main() -> ! {
 
     let mut last_link_up = false;
 
-    let mut bare_phy = BarePhy::new(mac.with_mii(mdio, mdc), PHY_ADDR, Default::default());
+    #[cfg(feature = "f-series")]
+    let mut bare_phy = BarePhy::new(_mac.with_mii(mdio, mdc), PHY_ADDR, Default::default());
 
     loop {
+        #[cfg(feature = "f-series")]
         let link_up = bare_phy.phy_link_up();
 
+        #[cfg(feature = "stm32h7xx-hal")]
+        let link_up = true;
+
         if link_up != last_link_up {
             if link_up {
                 defmt::info!("Ethernet: link detected");
@@ -129,7 +142,7 @@ fn main() -> ! {
                     defmt::info!("ARP sent");
                 }
                 Err(TxError::WouldBlock) => {
-                    defmt::panic!("ARP failed. {}", dma.tx_state())
+                    defmt::info!("ARP failed. {}", dma.tx_state())
                 }
             }
         } else {

examples/common.rs

@@ -4,10 +4,13 @@
 //!
 //! Note that this module isn't an example by itself.
 
-use stm32_eth::{
-    hal::{gpio::GpioExt, rcc::Clocks},
-    PartsIn,
-};
+use stm32_eth::{hal::gpio::GpioExt, PartsIn};
+
+#[cfg(feature = "f-series")]
+use stm32_eth::hal::rcc::Clocks;
+
+#[cfg(feature = "stm32h7xx-hal")]
+use stm32_eth::hal::rcc::CoreClocks as Clocks;
 
 pub use pins::{setup_pins, Gpio};
 
@@ -23,6 +26,9 @@ pub fn setup_peripherals(p: stm32_eth::stm32::Peripherals) -> (Clocks, Gpio, Par
     let ethernet = PartsIn {
         dma: p.ETHERNET_DMA,
         mac: p.ETHERNET_MAC,
+        #[cfg(feature = "stm32h7xx-hal")]
+        mtl: p.ETHERNET_MTL,
+        #[cfg(feature = "f-series")]
         mmc: p.ETHERNET_MMC,
         #[cfg(feature = "ptp")]
         ptp: p.ETHERNET_PTP,
@@ -99,6 +105,40 @@ pub fn setup_peripherals(p: stm32_eth::stm32::Peripherals) -> (Clocks, Gpio, Par
 
         (clocks, gpio, ethernet)
     }
+
+    #[cfg(feature = "stm32h7xx-hal")]
+    {
+        use stm32_eth::hal::pwr::PwrExt;
+
+        let rcc = p.RCC.constrain();
+        let pwr = p.PWR.constrain();
+
+        let syscfg = p.SYSCFG;
+
+        let pwrcfg = pwr.vos0(&syscfg).freeze();
+
+        let rcc = rcc.hclk(240.MHz());
+
+        let rcc = if cfg!(hse = "bypass") {
+            rcc.bypass_hse().use_hse(8.MHz())
+        } else if cfg!(hse = "oscillator") {
+            rcc.use_hse(8.MHz())
+        } else {
+            rcc
+        };
+
+        let ccdr = rcc.freeze(pwrcfg, &syscfg);
+        let clocks = ccdr.clocks;
+
+        let gpio = Gpio {
+            gpioa: p.GPIOA.split(ccdr.peripheral.GPIOA),
+            gpiob: p.GPIOB.split(ccdr.peripheral.GPIOB),
+            gpioc: p.GPIOC.split(ccdr.peripheral.GPIOC),
+            gpiog: p.GPIOG.split(ccdr.peripheral.GPIOG),
+        };
+
+        (clocks, gpio, ethernet)
+    }
 }
 
 pub use pins::*;
@@ -280,6 +320,75 @@ mod pins {
     }
 }
 
+#[cfg(feature = "stm32h7xx-hal")]
+mod pins {
+    use stm32_eth::{
+        hal::gpio::{Input, PushPull, *},
+        EthPins,
+    };
+
+    pub struct Gpio {
+        pub gpioa: gpioa::Parts,
+        pub gpiob: gpiob::Parts,
+        pub gpioc: gpioc::Parts,
+        pub gpiog: gpiog::Parts,
+    }
+
+    pub type RefClk = PA1<Input>;
+    pub type Crs = PA7<Input>;
+    pub type TxEn = PG11<Input>;
+    pub type TxD0 = PG13<Input>;
+    pub type TxD1 = PB13<Input>;
+    pub type RxD0 = PC4<Input>;
+    pub type RxD1 = PC5<Input>;
+
+    pub type Pps = PB5<Output<PushPull>>;
+
+    pub type Mdio = ();
+    pub type Mdc = ();
+
+    pub fn setup_pins(
+        gpio: Gpio,
+    ) -> (
+        EthPins<RefClk, Crs, TxEn, TxD0, TxD1, RxD0, RxD1>,
+        Mdio,
+        Mdc,
+        Pps,
+    ) {
+        let Gpio {
+            gpioa,
+            gpiob,
+            gpioc,
+            gpiog,
+        } = gpio;
+
+        let ref_clk = gpioa.pa1.into_input();
+        let crs = gpioa.pa7.into_input();
+        let rx_d0 = gpioc.pc4.into_input();
+        let rx_d1 = gpioc.pc5.into_input();
+        let tx_en = gpiog.pg11.into_input();
+        let tx_d0 = gpiog.pg13.into_input();
+        let tx_d1 = gpiob.pb13.into_input();
+
+        let mdc = ();
+        let mdio = ();
+
+        let pps = gpiob.pb5.into_push_pull_output();
+
+        let pins = EthPins {
+            ref_clk,
+            crs,
+            tx_en,
+            tx_d0,
+            tx_d1,
+            rx_d0,
+            rx_d1,
+        };
+
+        (pins, mdio, mdc, pps)
+    }
+}
+
 use ieee802_3_miim::{
     phy::{
         lan87xxa::{LAN8720A, LAN8742A},

memory.x

@@ -1,5 +1,63 @@
 MEMORY
 {
-  FLASH       : ORIGIN = 0x08000000, LENGTH = 128k
-  RAM         : ORIGIN = 0x20000000, LENGTH = 32K
+  /* FLASH and RAM are mandatory memory regions */
+
+  /* STM32H742xI/743xI/753xI       */
+  /* STM32H745xI/747xI/755xI/757xI */
+  /* STM32H7A3xI/7B3xI             */
+  FLASH  : ORIGIN = 0x08000000, LENGTH = 1M
+
+  /* STM32H742xG/743xG       */
+  /* STM32H745xG/STM32H747xG */
+  /* STM32H7A3xG             */
+  /* FLASH  : ORIGIN = 0x08000000, LENGTH = 512K */
+  /* FLASH1 : ORIGIN = 0x08100000, LENGTH = 512K */
+
+  /* STM32H750xB   */
+  /* STM32H7B0     */
+  /* FLASH  : ORIGIN = 0x08000000, LENGTH = 128K */
+
+  /* DTCM  */
+  RAM    : ORIGIN = 0x20000000, LENGTH = 128K
+
+  /* AXISRAM */
+  AXISRAM : ORIGIN = 0x24000000, LENGTH = 512K
+
+  /* SRAM */
+  SRAM1 : ORIGIN = 0x30000000, LENGTH = 128K
+  SRAM2 : ORIGIN = 0x30020000, LENGTH = 128K
+  /* SRAM3 : ORIGIN = 0x30040000, LENGTH = 32K */
+  SRAM4 : ORIGIN = 0x38000000, LENGTH = 64K
+
+  /* Backup SRAM */
+  BSRAM : ORIGIN = 0x38800000, LENGTH = 4K
+
+  /* Instruction TCM */
+  ITCM  : ORIGIN = 0x00000000, LENGTH = 64K
 }
+
+/* The location of the stack can be overridden using the
+   `_stack_start` symbol.  Place the stack at the end of RAM */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+
+/* The location of the .text section can be overridden using the
+   `_stext` symbol.  By default it will place after .vector_table */
+/* _stext = ORIGIN(FLASH) + 0x40c; */
+
+/* These sections are used for some of the examples */
+SECTIONS {
+  .axisram (NOLOAD) : ALIGN(8) {
+    *(.axisram .axisram.*);
+    . = ALIGN(8);
+    } > AXISRAM
+  /* The SRAM1 and SRAM2 section are commonly used as the stack and heap for the
+     CM4 core in dualcore versions and should thus not be used in examples*/
+  .sram4 (NOLOAD) : ALIGN(4) {
+    *(.sram4 .sram4.*);
+    . = ALIGN(4);
+    } > SRAM4
+  .sram1 (NOLOAD) : ALIGN(4) {
+    *(.sram1 .sram1.*);
+    . = ALIGN(4);
+  } > SRAM1
+};