Fix #57

We introduce an additional abstraction layer that, for STM32F4 parts, introduces a delay
before writing to a register. This is to prevent the same register from being
written to twice within 4 cycles of REF_CLK. It assumes worst-case setups (180 MHz
clock, and 25 MHz REF_CLK), which comes out to a minimum of 30 cycles of delay.

On F1 and F7 parts, the existing ETHERNET_DMA and ETHERNET_MAC are simply re-exported
without any modifications

Author: datdenkikniet

Cargo.toml

@@ -23,6 +23,7 @@ volatile-register = "0.2"
 aligned = "0.4"
 stm32f7xx-hal = { version = "0.7.0", optional = true }
 stm32f4xx-hal = { version = "0.14", optional = true }
+stm32f4 = { version = "0.15", optional = true }
 stm32f1xx-hal = { version = "0.10", optional = true }
 ieee802_3_miim = "0.7"
 cortex-m = "0.7"
@@ -41,14 +42,14 @@ fence = []
 
 stm32f107 = ["stm32f1xx-hal/stm32f107", "device-selected"]
 
-stm32f407 = ["stm32f4xx-hal/stm32f407", "device-selected"]
-stm32f417 = ["stm32f4xx-hal/stm32f417", "device-selected"]
-stm32f427 = ["stm32f4xx-hal/stm32f427", "device-selected"]
-stm32f429 = ["stm32f4xx-hal/stm32f429", "device-selected"]
-stm32f437 = ["stm32f4xx-hal/stm32f437", "device-selected"]
-stm32f439 = ["stm32f4xx-hal/stm32f439", "device-selected"]
-stm32f469 = ["stm32f4xx-hal/stm32f469", "device-selected"]
-stm32f479 = ["stm32f4xx-hal/stm32f479", "device-selected"]
+stm32f407 = ["stm32f4xx-hal/stm32f407", "stm32f4", "device-selected"]
+stm32f417 = ["stm32f4xx-hal/stm32f417", "stm32f4", "device-selected"]
+stm32f427 = ["stm32f4xx-hal/stm32f427", "stm32f4", "device-selected"]
+stm32f429 = ["stm32f4xx-hal/stm32f429", "stm32f4", "device-selected"]
+stm32f437 = ["stm32f4xx-hal/stm32f437", "stm32f4", "device-selected"]
+stm32f439 = ["stm32f4xx-hal/stm32f439", "stm32f4", "device-selected"]
+stm32f469 = ["stm32f4xx-hal/stm32f469", "stm32f4", "device-selected"]
+stm32f479 = ["stm32f4xx-hal/stm32f479", "stm32f4", "device-selected"]
 
 stm32f745 = ["stm32f7xx-hal/stm32f745", "device-selected", "fence"]
 stm32f746 = ["stm32f7xx-hal/stm32f746", "device-selected", "fence"]

src/dma.rs

@@ -1,8 +1,11 @@
+use core::borrow::Borrow;
+
 use cortex_m::peripheral::NVIC;
 
 use crate::{
+    peripherals::{ETHERNET_DMA, ETHERNET_MAC},
     rx::{RxPacket, RxRing},
-    stm32::{Interrupt, ETHERNET_DMA, ETHERNET_MAC},
+    stm32::Interrupt,
     tx::TxRing,
     RxError, RxRingEntry, TxError, TxRingEntry,
 };
@@ -128,8 +131,9 @@ impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {
 
     /// Calls [`eth_interrupt_handler()`](fn.eth_interrupt_handler.html)
     pub fn interrupt_handler(&self) -> InterruptReasonSummary {
-        let status = eth_interrupt_handler(&self.eth_dma);
-        eth_interrupt_handler(&self.eth_dma);
+        let eth_dma = &self.eth_dma;
+        let status = eth_interrupt_handler_impl(eth_dma);
+        eth_interrupt_handler_impl(eth_dma);
         status
     }
 
@@ -181,7 +185,12 @@ pub struct InterruptReasonSummary {
 ///
 /// * Via the [`EthernetDMA`](struct.EthernetDMA.html) driver instance that your interrupt handler has access to.
 /// * By unsafely getting `Peripherals`.
-pub fn eth_interrupt_handler(eth_dma: &ETHERNET_DMA) -> InterruptReasonSummary {
+pub fn eth_interrupt_handler(eth_dma: &crate::hal::pac::ETHERNET_DMA) -> InterruptReasonSummary {
+    let eth_dma: &ETHERNET_DMA = eth_dma.borrow();
+    eth_interrupt_handler_impl(eth_dma)
+}
+
+fn eth_interrupt_handler_impl(eth_dma: &ETHERNET_DMA) -> InterruptReasonSummary {
     let status = eth_dma.dmasr.read();
 
     let status = InterruptReasonSummary {

src/lib.rs

@@ -67,6 +67,9 @@ use setup::{
     AlternateVeryHighSpeed, RmiiCrsDv, RmiiRefClk, RmiiRxD0, RmiiRxD1, RmiiTxD0, RmiiTxD1, RmiiTxEN,
 };
 
+#[cfg(feature = "device-selected")]
+mod peripherals;
+
 #[cfg(all(feature = "smoltcp-phy", feature = "device-selected"))]
 pub use smoltcp;
 #[cfg(all(feature = "smoltcp-phy", feature = "device-selected"))]
@@ -123,11 +126,13 @@ where
     // Set up the clocks and reset the MAC periperhal
     setup::setup();
 
+    let eth_mac = eth_mac.into();
+
     // Congfigure and start up the ethernet DMA.
     // Note: this _must_ happen before configuring the MAC.
     // It's not entirely clear why, but no interrupts are
     // generated if the order is reversed.
-    let dma = EthernetDMA::new(eth_dma, &eth_mac, rx_buffer, tx_buffer);
+    let dma = EthernetDMA::new(eth_dma.into(), &eth_mac, rx_buffer, tx_buffer);
 
     // Configure the ethernet MAC
     let mac = EthernetMAC::new(eth_mac, eth_mmc, &dma, clocks, Speed::FullDuplexBase100Tx)?;
@@ -184,11 +189,13 @@ where
     // Set up the clocks and reset the MAC periperhal
     setup::setup();
 
+    let eth_mac = eth_mac.into();
+
     // Congfigure and start up the ethernet DMA.
     // Note: this _must_ happen before configuring the MAC.
     // It's not entirely clear why, but no interrupts are
     // generated if the order is reversed.
-    let dma = EthernetDMA::new(eth_dma, &eth_mac, rx_buffer, tx_buffer);
+    let dma = EthernetDMA::new(eth_dma.into(), &eth_mac, rx_buffer, tx_buffer);
 
     // Configure the ethernet MAC
     let mac = EthernetMAC::new(eth_mac, eth_mmc, &dma, clocks, Speed::FullDuplexBase100Tx)?

src/mac/miim.rs

@@ -2,10 +2,7 @@ pub use ieee802_3_miim::Miim;
 
 pub use ieee802_3_miim::*;
 
-use crate::{
-    stm32::{ethernet_mac::MACMIIAR, ETHERNET_MAC},
-    EthernetMAC,
-};
+use crate::{peripherals::ETHERNET_MAC, stm32::ethernet_mac::MACMIIAR, EthernetMAC};
 
 /// MDIO pin types.
 ///

src/mac/mod.rs

@@ -2,11 +2,7 @@
 
 use core::ops::{Deref, DerefMut};
 
-use crate::{
-    hal::rcc::Clocks,
-    stm32::{ETHERNET_MAC, ETHERNET_MMC},
-    EthernetDMA,
-};
+use crate::{hal::rcc::Clocks, peripherals::ETHERNET_MAC, stm32::ETHERNET_MMC, EthernetDMA};
 
 mod miim;
 pub use miim::*;