Merge pull request #13 from dtjones190/master

Added STM32F767 Support

Author: thalesfragoso

.gitignore

@@ -1,2 +1,2 @@
 target/
-Cargo.lock
+Cargo.lock

.travis.yml

@@ -21,5 +21,24 @@ matrix:
       env: FEATURES='stm32f429' ARGS="--release --target=thumbv7em-none-eabihf --example=pktgen"
     - rust: nightly
       env: FEATURES='stm32f429 smoltcp-phy smoltcp-log smoltcp-verbose' ARGS="--release --target=thumbv7em-none-eabihf --example=ip"
+    - rust: nightly
+      env: FEATURES='stm32f745'
+    - rust: nightly
+      env: FEATURES='stm32f746'
+    - rust: nightly
+      env: FEATURES='stm32f756'
+    - rust: nightly
+      env: FEATURES='stm32f765'
+    - rust: nightly
+      env: FEATURES='stm32f767'
+    - rust: nightly
+      env: FEATURES='stm32f769'
+    - rust: nightly
+      env: FEATURES='stm32f777'
+    - rust: nightly
+      env: FEATURES='stm32f778'
+    - rust: nightly
+      env: FEATURES='stm32f779'
+      
 script:
   - "cargo build --target=`uname -m`-unknown-linux-gnu --no-default-features --features \"$FEATURES\""

Cargo.toml

@@ -5,7 +5,7 @@ description = "Embedded Rust Ethernet driver for the STM32 MCU series"
 license = "Apache-2.0"
 authors = ["Astro <[email protected]>"]
 version = "0.2.0"
-keywords = ["ethernet", "eth", "stm32", "stm32f4"]
+keywords = ["ethernet", "eth", "stm32", "stm32f4", "stm32f7"]
 repository = "https://github.com/stm32-rs/stm32-eth"
 documentation = "https://docs.rs/stm32-eth/"
 edition = "2018"
@@ -20,7 +20,9 @@ features = [ "smoltcp-phy", "stm32f429" ]
 [dependencies]
 volatile-register = "0.2"
 aligned = "0.3"
-stm32f4xx-hal = "0.8.3"
+stm32f7xx-hal = {version = "0.2.0", optional = true}
+stm32f4xx-hal = {version = "0.8.3", optional = true}
+cortex-m = "0.6.0"
 
 smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "proto-ipv6", "socket-icmp", "socket-udp", "socket-tcp", "ethernet"], optional = true }
 log = { version = "0.4", optional = true }
@@ -35,6 +37,17 @@ stm32f437 = ["stm32f4xx-hal/stm32f437", "device-selected"]
 stm32f439 = ["stm32f4xx-hal/stm32f439", "device-selected"]
 stm32f469 = ["stm32f4xx-hal/stm32f469", "device-selected"]
 stm32f479 = ["stm32f4xx-hal/stm32f479", "device-selected"]
+
+stm32f745 = ["stm32f7xx-hal/stm32f745", "device-selected"]
+stm32f746 = ["stm32f7xx-hal/stm32f746", "device-selected"]
+stm32f756 = ["stm32f7xx-hal/stm32f756", "device-selected"]
+stm32f765 = ["stm32f7xx-hal/stm32f765", "device-selected"]
+stm32f767 = ["stm32f7xx-hal/stm32f767", "device-selected"]
+stm32f769 = ["stm32f7xx-hal/stm32f769", "device-selected"]
+stm32f777 = ["stm32f7xx-hal/stm32f777", "device-selected"]
+stm32f778 = ["stm32f7xx-hal/stm32f778", "device-selected"]
+stm32f779 = ["stm32f7xx-hal/stm32f779", "device-selected"]
+
 smoltcp-phy = ["smoltcp"]
 smoltcp-log = ["log", "smoltcp/log"]
 smoltcp-verbose = ["smoltcp/verbose"]

README.md

@@ -5,9 +5,15 @@
 ## Supported microcontrollers
 
 * STM32F4xx
+* STM32F7xx
 
 Please send pull requests.
 
+## Building Examples
+```
+cargo build --example="pktgen" --features="stm32f429"
+cargo build --example="ip" --features="stm32f429" --features="smoltcp-phy smoltcp-log smoltcp-verbose"
+```
 
 ## Usage
 
@@ -16,13 +22,21 @@ Add to the `[dependencies]` section in your `Cargo.toml`:
 stm32f4xx-hal = { version = "0.8.3", features = ["stm32f429"] }
 stm32-eth = { version = "0.2.0", features = ["stm32f429"] }
 ```
+or
+```rust
+stm32f7xx-hal = { version = "0.2.0", features = ["stm32f767"] }
+stm32-eth = { version = "0.2.0", features = ["stm32f767"]}
+```
 
 In `src/main.rs` add:
 ```rust
-use stm32f4xx_hal::{
-    gpio::GpioExt,
+use stm32_eth::{
+    hal::gpio::GpioExt,
+    hal::rcc::RccExt,
     stm32::Peripherals,
 };
+
+
 use stm32_eth::{Eth, RingEntry};
 
 fn main() {

examples/ip.rs

@@ -5,9 +5,10 @@ extern crate panic_itm;
 
 use cortex_m::asm;
 use cortex_m_rt::{entry, exception};
-use stm32f4xx_hal::{
-    gpio::GpioExt,
-    prelude::*,
+use stm32_eth::{
+    hal::gpio::GpioExt,
+    hal::rcc::RccExt,
+    hal::time::U32Ext,
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
 };
 

examples/pktgen.rs

@@ -9,9 +9,10 @@ use cortex_m_rt::{entry, exception};
 
 use cortex_m::asm;
 use cortex_m::interrupt::Mutex;
-use stm32f4xx_hal::{
-    gpio::GpioExt,
-    prelude::*,
+use stm32_eth::{
+    hal::gpio::GpioExt,
+    hal::rcc::RccExt,
+    hal::time::U32Ext,
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
 };
 

src/lib.rs

@@ -1,13 +1,23 @@
 #![no_std]
 
 /// Re-export
+#[cfg(feature = "stm32f7xx-hal")]
+pub use stm32f7xx_hal as hal;
+/// Re-export
+#[cfg(feature = "stm32f7xx-hal")]
+pub use stm32f7xx_hal::device as stm32;
+
+/// Re-export
+#[cfg(feature = "stm32f4xx-hal")]
 pub use stm32f4xx_hal as hal;
 /// Re-export
+#[cfg(feature = "stm32f4xx-hal")]
 pub use stm32f4xx_hal::stm32;
-use stm32f4xx_hal::{
-    rcc::Clocks,
-    stm32::{Interrupt, ETHERNET_DMA, ETHERNET_MAC, NVIC},
-};
+
+use hal::rcc::Clocks;
+use stm32::{Interrupt, ETHERNET_DMA, ETHERNET_MAC, NVIC};
+
+use cortex_m::asm;
 
 pub mod phy;
 use phy::{Phy, PhyStatus};
@@ -78,8 +88,10 @@ impl<'rx, 'tx> Eth<'rx, 'tx> {
     ///
     /// Make sure that the buffers reside in a memory region that is
     /// accessible by the peripheral. Core-Coupled Memory (CCM) is
-    /// usually not accessible. Also, HCLK must be between 25MHz and 168MHz to use the ethernet
-    /// peripheral.
+    /// usually not accessible. HCLK must be between 25MHz and 168MHz for STM32F4xx 
+    /// or 25MHz to 216MHz for STM32F7xx.
+    ///
+    /// Uses an interrupt free critical section to turn on the ethernet clock for STM32F7xx.
     ///
     /// Other than that, initializes and starts the Ethernet hardware
     /// so that you can [`send()`](#method.send) and
@@ -125,7 +137,10 @@ impl<'rx, 'tx> Eth<'rx, 'tx> {
             100_000_000..=149_999_999 => ETH_MACMIIAR_CR_HCLK_DIV_62,
             25_000_000..=34_999_999 => ETH_MACMIIAR_CR_HCLK_DIV_16,
             35_000_000..=59_999_999 => ETH_MACMIIAR_CR_HCLK_DIV_26,
+            #[cfg(feature = "stm32f4xx-hal")]
             150_000_000..=168_000_000 => ETH_MACMIIAR_CR_HCLK_DIV_102,
+            #[cfg(feature = "stm32f7xx-hal")]
+            150_000_000..=216_000_000 => ETH_MACMIIAR_CR_HCLK_DIV_102,
             _ => return Err(WrongClock),
         };
         self.reset_dma_and_wait();
@@ -249,10 +264,8 @@ impl<'rx, 'tx> Eth<'rx, 'tx> {
         });
 
         // Enable ethernet interrupts
-        let interrupt = Interrupt::ETH;
-
         unsafe {
-            NVIC::unmask(interrupt);
+            NVIC::unmask(Interrupt::ETH);
         }
     }
 
@@ -301,6 +314,8 @@ impl<'rx, 'tx> Eth<'rx, 'tx> {
         f: F,
     ) -> Result<R, TxError> {
         let result = self.tx_ring.send(length, f);
+        //Make sure the memory write occurs before triggering DMA
+        asm::dmb();
         self.tx_ring.demand_poll(&self.eth_dma);
         result
     }

src/phy.rs

@@ -1,5 +1,11 @@
+#[cfg(feature = "stm32f4xx-hal")]
+use stm32f4xx_hal::stm32;
+#[cfg(feature = "stm32f7xx-hal")]
+use stm32f7xx_hal::device as stm32;
+
+use stm32::ethernet_mac::{MACMIIAR, MACMIIDR};
+
 use core::option::Option;
-use stm32f4xx_hal::stm32::ethernet_mac::{MACMIIAR, MACMIIDR};
 
 use crate::smi::SMI;
 

src/rx.rs

@@ -1,6 +1,12 @@
+#[cfg(feature = "stm32f4xx-hal")]
+use stm32f4xx_hal::stm32;
+#[cfg(feature = "stm32f7xx-hal")]
+use stm32f7xx_hal::device as stm32;
+
+use stm32::ETHERNET_DMA;
+
 use core::default::Default;
 use core::ops::{Deref, DerefMut};
-use stm32f4xx_hal::stm32::ETHERNET_DMA;
 
 use crate::{
     desc::Descriptor,

src/setup.rs

@@ -1,4 +1,4 @@
-#[cfg(feature = "device-selected")]
+#[cfg(feature = "stm32f4xx-hal")]
 use stm32f4xx_hal::{
     bb,
     gpio::{
@@ -12,15 +12,31 @@ use stm32f4xx_hal::{
     stm32::{RCC, SYSCFG},
 };
 
-const SYSCFG_BIT: u8 = 14;
-const ETH_MAC_BIT: u8 = 25;
-const ETH_TX_BIT: u8 = 26;
-const ETH_RX_BIT: u8 = 27;
-const MII_RMII_BIT: u8 = 23;
+#[cfg(feature = "stm32f7xx-hal")]
+use cortex_m::interrupt;
+#[cfg(feature = "stm32f7xx-hal")]
+use stm32f7xx_hal::{
+    device::{RCC, SYSCFG},
+    gpio::{
+        gpioa::{PA1, PA2, PA7},
+        gpiob::{PB11, PB12, PB13},
+        gpioc::{PC1, PC4, PC5},
+        gpiog::{PG11, PG13, PG14},
+        Floating, Input,
+        Speed::VeryHigh,
+    },
+};
 
 // Enable syscfg and ethernet clocks. Reset the Ethernet MAC.
 pub(crate) fn setup() {
+    #[cfg(feature = "stm32f4xx-hal")]
     unsafe {
+        const SYSCFG_BIT: u8 = 14;
+        const ETH_MAC_BIT: u8 = 25;
+        const ETH_TX_BIT: u8 = 26;
+        const ETH_RX_BIT: u8 = 27;
+        const MII_RMII_BIT: u8 = 23;
+
         //NOTE(unsafe) This will only be used for atomic writes with no side-effects
         let rcc = &*RCC::ptr();
         let syscfg = &*SYSCFG::ptr();
@@ -45,6 +61,38 @@ pub(crate) fn setup() {
         bb::set(&rcc.ahb1rstr, ETH_MAC_BIT);
         bb::clear(&rcc.ahb1rstr, ETH_MAC_BIT);
     }
+    #[cfg(feature = "stm32f7xx-hal")]
+    //stm32f7xx-hal does not currently have bitbanding
+    interrupt::free(|_| unsafe {
+        //NOTE(unsafe) Interrupt free and we only modify mac bits
+        let rcc = &*RCC::ptr();
+        let syscfg = &*SYSCFG::ptr();
+        // enable syscfg clock
+        rcc.apb2enr.modify(|_, w| w.syscfgen().set_bit());
+
+        if rcc.ahb1enr.read().ethmacen().bit_is_set() {
+            // pmc must be changed with the ethernet controller disabled or under reset
+            rcc.ahb1enr.modify(|_, w| w.ethmacen().clear_bit());
+        }
+
+        // select MII or RMII mode
+        // 0 = MII, 1 = RMII
+        syscfg.pmc.modify(|_, w| w.mii_rmii_sel().set_bit());
+
+        // enable ethernet clocks
+        rcc.ahb1enr.modify(|_, w| {
+            w.ethmacen()
+                .set_bit()
+                .ethmactxen()
+                .set_bit()
+                .ethmacrxen()
+                .set_bit()
+        });
+
+        //reset pulse
+        rcc.ahb1rstr.modify(|_, w| w.ethmacrst().set_bit());
+        rcc.ahb1rstr.modify(|_, w| w.ethmacrst().clear_bit());
+    });
 }
 
 /// RMII Reference Clock.