Switch to ieee802_3_miim for provisioning of MIIM

Author: Johannes Draaijer

Cargo.toml

@@ -23,6 +23,7 @@ aligned = "0.4"
 stm32f7xx-hal = { version = "0.7.0", optional = true }
 stm32f4xx-hal = { version = "0.13", optional = true }
 stm32f1xx-hal = { version = "0.9", optional = true }
+ieee802_3_miim = { version = "0.6", optional = true }
 cortex-m = "0.7"
 log = { version = "0.4", optional = true }
 
@@ -38,11 +39,9 @@ default-features = false
 optional = true
 
 [features]
-default = [ "phy-lan87xxa" ]
+default = [ "ieee802_3_miim" ]
 device-selected = []
 fence = []
-phy = [ "num_enum" ]
-phy-lan87xxa = [ "phy" ]
 
 stm32f107 = ["stm32f1xx-hal/stm32f107", "device-selected"]
 

examples/arp-smoltcp.rs

@@ -18,21 +18,19 @@ use cortex_m::interrupt::Mutex;
 use cortex_m_rt::{entry, exception};
 use cortex_m_semihosting::hprintln;
 use fugit::RateExtU32;
+use ieee802_3_miim::Phy;
 use smoltcp::wire::{
     ArpOperation, ArpPacket, ArpRepr, EthernetAddress, EthernetFrame, EthernetProtocol,
     EthernetRepr, Ipv4Address,
 };
 use stm32_eth::{
     hal::gpio::{GpioExt, Speed},
     hal::rcc::RccExt,
-    mac::{MdcPin, MdioPin, Smi, SerialManagement},
+    mac::phy::bare::BarePhy,
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
 };
 use stm32_eth::{EthPins, RingEntry, TxError};
 
-const PHY_REG_BSR: u8 = 0x01;
-const PHY_REG_BSR_UP: u16 = 1 << 2;
-
 const PHY_ADDR: u8 = 0;
 
 static TIME: Mutex<RefCell<usize>> = Mutex::new(RefCell::new(0));
@@ -75,7 +73,7 @@ fn main() -> ! {
 
     let mut rx_ring: [RingEntry<_>; 16] = Default::default();
     let mut tx_ring: [RingEntry<_>; 8] = Default::default();
-    let (mut eth_dma, mut eth_mac) = stm32_eth::new(
+    let (mut eth_dma, eth_mac) = stm32_eth::new(
         p.ETHERNET_MAC,
         p.ETHERNET_MMC,
         p.ETHERNET_DMA,
@@ -89,8 +87,10 @@ fn main() -> ! {
 
     let mut last_link_up = false;
 
+    let mut bare_phy = BarePhy::new(eth_mac.with_smi(mdio, mdc), PHY_ADDR, Default::default());
+
     loop {
-        let link_up = link_detected(eth_mac.smi(&mut mdio, &mut mdc));
+        let link_up = bare_phy.phy_link_up();
 
         if link_up != last_link_up {
             if link_up {
@@ -179,12 +179,3 @@ fn ETH() {
     let p = unsafe { Peripherals::steal() };
     stm32_eth::eth_interrupt_handler(&p.ETHERNET_DMA);
 }
-
-fn link_detected<Mdio, Mdc>(smi: Smi<Mdio, Mdc>) -> bool
-where
-    Mdio: MdioPin,
-    Mdc: MdcPin,
-{
-    let status = smi.read(PHY_ADDR, PHY_REG_BSR);
-    (status & PHY_REG_BSR_UP) == PHY_REG_BSR_UP
-}

examples/arp.rs

@@ -20,17 +20,14 @@ use fugit::RateExtU32;
 use stm32_eth::{
     hal::gpio::{GpioExt, Speed},
     hal::rcc::RccExt,
-    mac::{self, SerialManagement},
+    mac::{phy::bare::BarePhy, Phy},
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
 };
 
 use cortex_m_semihosting::hprintln;
 
 use stm32_eth::{EthPins, RingEntry, TxError};
 
-const PHY_REG_BSR: u8 = 0x01;
-const PHY_REG_BSR_UP: u16 = 1 << 2;
-
 const PHY_ADDR: u8 = 0;
 
 static TIME: Mutex<RefCell<usize>> = Mutex::new(RefCell::new(0));
@@ -73,7 +70,7 @@ fn main() -> ! {
 
     let mut rx_ring: [RingEntry<_>; 16] = Default::default();
     let mut tx_ring: [RingEntry<_>; 8] = Default::default();
-    let (mut eth_dma, mut eth_mac) = stm32_eth::new(
+    let (mut eth_dma, eth_mac) = stm32_eth::new(
         p.ETHERNET_MAC,
         p.ETHERNET_MMC,
         p.ETHERNET_DMA,
@@ -87,8 +84,10 @@ fn main() -> ! {
 
     let mut last_link_up = false;
 
+    let mut bare_phy = BarePhy::new(eth_mac.with_smi(mdio, mdc), PHY_ADDR, Default::default());
+
     loop {
-        let link_up = link_detected(eth_mac.smi(&mut mdio, &mut mdc));
+        let link_up = bare_phy.phy_link_up();
 
         if link_up != last_link_up {
             if link_up {
@@ -177,12 +176,3 @@ fn ETH() {
     let p = unsafe { Peripherals::steal() };
     stm32_eth::eth_interrupt_handler(&p.ETHERNET_DMA);
 }
-
-fn link_detected<Mdio, Mdc>(smi: mac::Smi<Mdio, Mdc>) -> bool
-where
-    Mdio: mac::MdioPin,
-    Mdc: mac::MdcPin,
-{
-    let status = smi.read(PHY_ADDR, PHY_REG_BSR);
-    (status & PHY_REG_BSR_UP) == PHY_REG_BSR_UP
-}

examples/pktgen.rs

@@ -17,7 +17,7 @@ use fugit::RateExtU32;
 use stm32_eth::{
     hal::gpio::{GpioExt, Speed},
     hal::rcc::RccExt,
-    mac,
+    mac::{phy::bare::BarePhy, Phy},
     stm32::{interrupt, CorePeripherals, Peripherals, SYST},
 };
 
@@ -70,7 +70,7 @@ fn main() -> ! {
 
     let mut rx_ring: [RingEntry<_>; 16] = Default::default();
     let mut tx_ring: [RingEntry<_>; 8] = Default::default();
-    let (mut eth_dma, mut eth_mac) = stm32_eth::new(
+    let (mut eth_dma, eth_mac) = stm32_eth::new(
         p.ETHERNET_MAC,
         p.ETHERNET_MMC,
         p.ETHERNET_DMA,
@@ -90,6 +90,8 @@ fn main() -> ! {
     let mut tx_pkts = 0usize;
     let mut last_link_up = false;
 
+    let mut phy = BarePhy::new(eth_mac.with_smi(mdio, mdc), PHY_ADDR, Default::default());
+
     loop {
         let time: usize = cortex_m::interrupt::free(|cs| *TIME.borrow(cs).borrow());
 
@@ -115,7 +117,7 @@ fn main() -> ! {
         }
 
         // Link change detection
-        let link_up = link_detected(eth_mac.smi(&mut mdio, &mut mdc));
+        let link_up = phy.phy_link_up();
         if link_up != last_link_up {
             if link_up {
                 writeln!(stdout, "Ethernet: no link detected").unwrap();
@@ -151,7 +153,7 @@ fn main() -> ! {
 
         // fill tx queue
         const SIZE: usize = 1500;
-        if link_detected(eth_mac.smi(&mut mdio, &mut mdc)) {
+        if phy.phy_link_up() {
             'egress: loop {
                 let r = eth_dma.send(SIZE, |buf| {
                     buf[0..6].copy_from_slice(&DST_MAC);
@@ -213,14 +215,3 @@ fn ETH() {
     let p = unsafe { Peripherals::steal() };
     stm32_eth::eth_interrupt_handler(&p.ETHERNET_DMA);
 }
-
-fn link_detected<Mdio, Mdc>(smi: mac::Smi<Mdio, Mdc>) -> bool
-where
-    Mdio: mac::MdioPin,
-    Mdc: mac::MdcPin,
-{
-    const STATUS_REG_ADDR: u8 = 0x3;
-    const STATUS_REG_UP_MASK: u16 = 1 << 2;
-    let status = smi.read(PHY_ADDR, STATUS_REG_ADDR);
-    (status & STATUS_REG_UP_MASK) == STATUS_REG_UP_MASK
-}

src/lib.rs

@@ -3,7 +3,7 @@
 //! For initialisation, see [`new`], and [`new_with_smi`]
 #![no_std]
 
-use mac::EthernetMACWithSmi;
+use mac::EthernetMACWithMiim;
 /// Re-export
 #[cfg(feature = "stm32f7xx-hal")]
 pub use stm32f7xx_hal as hal;
@@ -52,11 +52,6 @@ mod smoltcp_phy;
 #[cfg(feature = "smoltcp-phy")]
 pub use smoltcp_phy::{EthRxToken, EthTxToken};
 
-#[cfg(feature = "phy")]
-mod phy;
-#[cfg(feature = "phy")]
-pub use phy::*;
-
 /// From the datasheet: *VLAN Frame maxsize = 1522*
 const MTU: usize = 1522;
 
@@ -152,7 +147,7 @@ pub fn new_with_smi<'rx, 'tx, REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1, MDIO, M
     pins: EthPins<REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1>,
     mdio: MDIO,
     mdc: MDC,
-) -> Result<(EthernetDMA<'rx, 'tx>, EthernetMACWithSmi<MDIO, MDC>), WrongClock>
+) -> Result<(EthernetDMA<'rx, 'tx>, EthernetMACWithMiim<MDIO, MDC>), WrongClock>
 where
     REFCLK: RmiiRefClk + AlternateVeryHighSpeed,
     CRS: RmiiCrsDv + AlternateVeryHighSpeed,

src/mac/smi.rs renamed to src/mac/miim.rs

@@ -1,26 +1,23 @@
+#[cfg(feature = "ieee802_3_miim")]
+pub use ieee802_3_miim::Miim;
+
+#[cfg(feature = "ieee802_3_miim")]
+pub use ieee802_3_miim::*;
+
 use crate::stm32::ethernet_mac::{MACMIIAR, MACMIIDR};
 
 /// MDIO pin types.
 pub unsafe trait MdioPin {}
 /// MDC pin types.
 pub unsafe trait MdcPin {}
 
-/// A trait used for implementing access to SMI
-/// peripherals/functionality
-pub trait SerialManagement {
-    /// Read an SMI register
-    fn read(&self, phy: u8, reg: u8) -> u16;
-    /// Write an SMI register
-    fn write(&mut self, phy: u8, reg: u8, data: u16);
-}
-
 #[inline(always)]
-fn smi_wait_ready(iar: &MACMIIAR) {
+fn miim_wait_ready(iar: &MACMIIAR) {
     while iar.read().mb().bit_is_set() {}
 }
 
 #[inline(always)]
-pub(crate) fn smi_write(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8, data: u16) {
+pub(crate) fn miim_write(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8, data: u16) {
     dr.write(|w| w.md().bits(data));
 
     iar.modify(|_, w| {
@@ -34,11 +31,11 @@ pub(crate) fn smi_write(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8, data: u
             .mb()
             .set_bit()
     });
-    smi_wait_ready(iar);
+    miim_wait_ready(iar);
 }
 
 #[inline(always)]
-pub(crate) fn smi_read(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8) -> u16 {
+pub(crate) fn miim_read(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8) -> u16 {
     iar.modify(|_, w| {
         w.pa()
             .bits(phy)
@@ -50,7 +47,7 @@ pub(crate) fn smi_read(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8) -> u16 {
             .mb()
             .set_bit()
     });
-    smi_wait_ready(iar);
+    miim_wait_ready(iar);
 
     // Return value:
     dr.read().md().bits()
@@ -60,28 +57,43 @@ pub(crate) fn smi_read(iar: &MACMIIAR, dr: &MACMIIDR, phy: u8, reg: u8) -> u16 {
 ///
 /// Borrows [`MACMIIAR`] and [`MACMIIDR`] from (ETHERNET_MAC)[`crate::stm32::ETHERNET_MAC`], and holds a mutable borrow
 /// to the SMI pins.
-pub struct Smi<'eth, 'pins, Mdio, Mdc> {
+pub struct Stm32Miim<'eth, 'pins, Mdio, Mdc> {
     macmiiar: &'eth MACMIIAR,
     macmiidr: &'eth MACMIIDR,
     _mdio: &'pins mut Mdio,
     _mdc: &'pins mut Mdc,
 }
 
-impl<'eth, 'pins, Mdio, Mdc> SerialManagement for Smi<'eth, 'pins, Mdio, Mdc>
+impl<'eth, 'pins, Mdio, Mdc> Stm32Miim<'eth, 'pins, Mdio, Mdc>
+where
+    Mdio: MdioPin,
+    Mdc: MdcPin,
+{
+    pub fn read(&mut self, phy: u8, reg: u8) -> u16 {
+        miim_read(&self.macmiiar, &self.macmiidr, phy, reg)
+    }
+
+    pub fn write(&mut self, phy: u8, reg: u8, data: u16) {
+        miim_write(&self.macmiiar, &self.macmiidr, phy, reg, data)
+    }
+}
+
+#[cfg(feature = "ieee802_3_miim")]
+impl<'eth, 'pins, Mdio, Mdc> Miim for Stm32Miim<'eth, 'pins, Mdio, Mdc>
 where
     Mdio: MdioPin,
     Mdc: MdcPin,
 {
-    fn read(&self, phy: u8, reg: u8) -> u16 {
-        smi_read(&self.macmiiar, &self.macmiidr, phy, reg)
+    fn read(&mut self, phy: u8, reg: u8) -> u16 {
+        self.read(phy, reg)
     }
 
     fn write(&mut self, phy: u8, reg: u8, data: u16) {
-        smi_write(&self.macmiiar, &self.macmiidr, phy, reg, data)
+        self.write(phy, reg, data)
     }
 }
 
-impl<'eth, 'pins, Mdio, Mdc> Smi<'eth, 'pins, Mdio, Mdc>
+impl<'eth, 'pins, Mdio, Mdc> Stm32Miim<'eth, 'pins, Mdio, Mdc>
 where
     Mdio: MdioPin,
     Mdc: MdcPin,