Add fence feature

Author: thalesfragoso

Cargo.toml

@@ -29,6 +29,8 @@ log = { version = "0.4", optional = true }
 
 [features]
 device-selected = []
+fence = []
+
 stm32f407 = ["stm32f4xx-hal/stm32f407", "device-selected"]
 stm32f417 = ["stm32f4xx-hal/stm32f417", "device-selected"]
 stm32f427 = ["stm32f4xx-hal/stm32f427", "device-selected"]
@@ -38,15 +40,15 @@ stm32f439 = ["stm32f4xx-hal/stm32f439", "device-selected"]
 stm32f469 = ["stm32f4xx-hal/stm32f469", "device-selected"]
 stm32f479 = ["stm32f4xx-hal/stm32f479", "device-selected"]
 
-stm32f745 = ["stm32f7xx-hal/stm32f745", "device-selected"]
-stm32f746 = ["stm32f7xx-hal/stm32f746", "device-selected"]
-stm32f756 = ["stm32f7xx-hal/stm32f756", "device-selected"]
-stm32f765 = ["stm32f7xx-hal/stm32f765", "device-selected"]
-stm32f767 = ["stm32f7xx-hal/stm32f767", "device-selected"]
-stm32f769 = ["stm32f7xx-hal/stm32f769", "device-selected"]
-stm32f777 = ["stm32f7xx-hal/stm32f777", "device-selected"]
-stm32f778 = ["stm32f7xx-hal/stm32f778", "device-selected"]
-stm32f779 = ["stm32f7xx-hal/stm32f779", "device-selected"]
+stm32f745 = ["stm32f7xx-hal/stm32f745", "device-selected", "fence"]
+stm32f746 = ["stm32f7xx-hal/stm32f746", "device-selected", "fence"]
+stm32f756 = ["stm32f7xx-hal/stm32f756", "device-selected", "fence"]
+stm32f765 = ["stm32f7xx-hal/stm32f765", "device-selected", "fence"]
+stm32f767 = ["stm32f7xx-hal/stm32f767", "device-selected", "fence"]
+stm32f769 = ["stm32f7xx-hal/stm32f769", "device-selected", "fence"]
+stm32f777 = ["stm32f7xx-hal/stm32f777", "device-selected", "fence"]
+stm32f778 = ["stm32f7xx-hal/stm32f778", "device-selected", "fence"]
+stm32f779 = ["stm32f7xx-hal/stm32f779", "device-selected", "fence"]
 
 smoltcp-phy = ["smoltcp"]
 smoltcp-log = ["log", "smoltcp/log"]

src/rx.rs

@@ -66,9 +66,19 @@ impl RxDescriptor {
 
     /// Pass ownership to the DMA engine
     fn set_owned(&mut self) {
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        #[cfg(feature = "fence")]
+        atomic::fence(Ordering::Release);
+
+        atomic::compiler_fence(Ordering::Release);
         unsafe {
             self.desc.modify(0, |w| w | RXDESC_0_OWN);
         }
+
+        // Used to flush the store buffer as fast as possible to make the buffer available for the
+        // DMA.
+        #[cfg(feature = "fence")]
+        atomic::fence(Ordering::SeqCst);
     }
 
     fn has_error(&self) -> bool {
@@ -125,7 +135,6 @@ impl RingDescriptor for RxDescriptor {
                 self.set_end_of_ring();
             }
         };
-        // There is already a fence before starting the DMA engine
         self.set_owned();
     }
 }
@@ -177,13 +186,6 @@ impl<'a> DerefMut for RxPacket<'a> {
 
 impl<'a> Drop for RxPacket<'a> {
     fn drop(&mut self) {
-        // "Preceding reads and writes cannot be moved past subsequent writes."
-        #[cfg(feature = "stm32f7xx-hal")]
-        atomic::fence(Ordering::Release);
-
-        #[cfg(not(feature = "stm32f7xx-hal"))]
-        atomic::compiler_fence(Ordering::Release);
-
         self.entry.desc_mut().set_owned();
     }
 }
@@ -230,12 +232,7 @@ impl<'a> RxRing<'a> {
         // Register RxDescriptor
         eth_dma.dmardlar.write(|w| w.srl().bits(ring_ptr as u32));
 
-        // "Preceding reads and writes cannot be moved past subsequent writes."
-        #[cfg(feature = "stm32f7xx-hal")]
-        atomic::fence(Ordering::Release);
-
-        // We don't need a compiler fence here because all interactions with `Descriptor` are
-        // volatiles
+        // We already have fences in `set_owned`, which is called in `setup`
 
         // Start receive
         eth_dma.dmaomr.modify(|_, w| w.sr().set_bit());
@@ -246,11 +243,6 @@ impl<'a> RxRing<'a> {
     /// Demand that the DMA engine polls the current `RxDescriptor`
     /// (when in `RunningState::Stopped`.)
     pub fn demand_poll(&self, eth_dma: &ETHERNET_DMA) {
-        // Prevent `set_owned` to me moved to after the poll
-        // "Preceding reads and writes cannot be moved past subsequent writes."
-        #[cfg(feature = "stm32f7xx-hal")]
-        atomic::fence(Ordering::Release);
-
         eth_dma.dmarpdr.write(|w| unsafe { w.rpd().bits(1) });
     }
 

src/tx.rs

@@ -63,9 +63,19 @@ impl TxDescriptor {
 
     /// Pass ownership to the DMA engine
     fn set_owned(&mut self) {
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        #[cfg(feature = "fence")]
+        atomic::fence(Ordering::Release);
+
+        atomic::compiler_fence(Ordering::Release);
         unsafe {
             self.desc.modify(0, |w| w | TXDESC_0_OWN);
         }
+
+        // Used to flush the store buffer as fast as possible to make the buffer available for the
+        // DMA.
+        #[cfg(feature = "fence")]
+        atomic::fence(Ordering::SeqCst);
     }
 
     #[allow(unused)]
@@ -155,13 +165,6 @@ impl<'a> DerefMut for TxPacket<'a> {
 impl<'a> TxPacket<'a> {
     // Pass to DMA engine
     pub fn send(self) {
-        // "Preceding reads and writes cannot be moved past subsequent writes."
-        #[cfg(feature = "stm32f7xx-hal")]
-        atomic::fence(Ordering::Release);
-
-        #[cfg(not(feature = "stm32f7xx-hal"))]
-        atomic::compiler_fence(Ordering::Release);
-
         self.entry.desc_mut().set_owned();
     }
 }
@@ -204,7 +207,7 @@ impl<'a> TxRing<'a> {
         eth_dma.dmatdlar.write(|w| w.stl().bits(ring_ptr as u32));
 
         // "Preceding reads and writes cannot be moved past subsequent writes."
-        #[cfg(feature = "stm32f7xx-hal")]
+        #[cfg(feature = "fence")]
         atomic::fence(Ordering::Release);
 
         // We don't need a compiler fence here because all interactions with `Descriptor` are
@@ -239,15 +242,6 @@ impl<'a> TxRing<'a> {
     /// Demand that the DMA engine polls the current `TxDescriptor`
     /// (when we just transferred ownership to the hardware).
     pub fn demand_poll(&self, eth_dma: &ETHERNET_DMA) {
-        // "Preceding reads and writes cannot be moved past subsequent writes."
-        #[cfg(feature = "stm32f7xx-hal")]
-        atomic::fence(Ordering::Release);
-
-        // We don't need a compiler fence here because all operations to the buffer were done before
-        // setting the owned bit (see fences in `TxPacket::send`). We also don't need a compiler
-        // fence between setting the owned bit and starting the poll, because setting the owned bit
-        // is a volatile operation
-
         eth_dma.dmatpdr.write(|w| w.tpd().poll());
     }