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Update Cargo.toml and README
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2 files changed

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Cargo.toml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ name = "stm32-eth"
44
description = "Embedded Rust Ethernet driver for the STM32 MCU series"
55
license = "Apache-2.0"
66
authors = ["Astro <[email protected]>"]
7-
version = "0.1.2"
7+
version = "0.2.0"
88
keywords = ["ethernet", "eth", "stm32", "stm32f4"]
99
repository = "https://github.com/stm32-rs/stm32-eth"
1010
documentation = "https://docs.rs/stm32-eth/"
@@ -40,7 +40,7 @@ smoltcp-log = ["log", "smoltcp/log"]
4040
smoltcp-verbose = ["smoltcp/verbose"]
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4242
[dev-dependencies]
43-
cortex-m = "0.5"
43+
cortex-m = "0.6.2"
4444
cortex-m-rt = "0.6"
4545
panic-itm = "0.4"
4646
cortex-m-semihosting = "0.3.5"

README.md

Lines changed: 31 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ Please send pull requests.
1313

1414
Add to the `[dependencies]` section in your `Cargo.toml`:
1515
```rust
16-
stm32f4xx-hal = { version = "*", features = ["stm32f429"] }
17-
stm32-eth = { version = "0.1.1", features = ["nucleo-f429zi"] }
16+
stm32f4xx-hal = { version = "0.8.3", features = ["stm32f429"] }
17+
stm32-eth = { version = "0.2.0", features = ["stm32f429"] }
1818
```
1919

2020
In `src/main.rs` add:
@@ -28,33 +28,45 @@ use stm32_eth::{Eth, RingEntry};
2828
fn main() {
2929
let p = Peripherals::take().unwrap();
3030

31-
// Setup pins and initialize clocks.
32-
stm32_eth::setup(&p.RCC, &p.SYSCFG);
31+
let rcc = p.RCC.constrain();
32+
// HCLK must be between 25MHz and 168MHz to use the ethernet peripheral
33+
let clocks = rcc.cfgr.sysclk(32.mhz()).hclk(32.mhz()).freeze();
34+
3335
let gpioa = p.GPIOA.split();
3436
let gpiob = p.GPIOB.split();
3537
let gpioc = p.GPIOC.split();
3638
let gpiog = p.GPIOG.split();
37-
stm32_eth::setup_pins(
38-
gpioa.pa1, gpioa.pa2, gpioa.pa7, gpiob.pb13, gpioc.pc1,
39-
gpioc.pc4, gpioc.pc5, gpiog.pg11, gpiog.pg13
40-
);
41-
// Allocate the ring buffers
42-
let mut rx_ring: [RingEntry<_>; 8] = Default::default();
43-
let mut tx_ring: [RingEntry<_>; 2] = Default::default();
44-
// Instantiate driver
45-
let mut eth = Eth::new(
46-
p.ETHERNET_MAC, p.ETHERNET_DMA,
47-
&mut rx_ring[..], &mut tx_ring[..]
48-
);
49-
// If you have a handler, enable interrupts
50-
eth.enable_interrupt(&mut cp.NVIC);
5139

40+
let eth_pins = EthPins {
41+
ref_clk: gpioa.pa1,
42+
md_io: gpioa.pa2,
43+
md_clk: gpioc.pc1,
44+
crs: gpioa.pa7,
45+
tx_en: gpiog.pg11,
46+
tx_d0: gpiog.pg13,
47+
tx_d1: gpiob.pb13,
48+
rx_d0: gpioc.pc4,
49+
rx_d1: gpioc.pc5,
50+
};
51+
52+
let mut rx_ring: [RingEntry<_>; 16] = Default::default();
53+
let mut tx_ring: [RingEntry<_>; 8] = Default::default();
54+
let mut eth = Eth::new(
55+
p.ETHERNET_MAC,
56+
p.ETHERNET_DMA,
57+
&mut rx_ring[..],
58+
&mut tx_ring[..],
59+
PhyAddress::_0,
60+
clocks,
61+
eth_pins,
62+
)
63+
.unwrap();
64+
eth.enable_interrupt();
5265

5366
if let Ok(pkt) = eth.recv_next() {
5467
// handle received pkt
5568
}
5669

57-
5870
eth.send(size, |buf| {
5971
// write up to `size` bytes into buf before it is being sent
6072
}).expect("send");

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