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update PAC version
1 parent 7a348ed commit 2d433f6

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19 files changed

+337
-338
lines changed

19 files changed

+337
-338
lines changed

‎src/analog/adc.rs‎

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ impl Adc {
118118
// Enable ADC clocks
119119
ADC::enable(rcc);
120120

121-
adc.cr.modify(|_, w| w.advregen().set_bit());
121+
adc.cr().modify(|_, w| w.advregen().set_bit());
122122

123123
Self {
124124
rb: adc,
@@ -134,12 +134,12 @@ impl Adc {
134134
match clock_source {
135135
ClockSource::Pclk(div) => self
136136
.rb
137-
.cfgr2
137+
.cfgr2()
138138
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) }),
139139
ClockSource::Async(div) => {
140-
self.rb.cfgr2.modify(|_, w| unsafe { w.ckmode().bits(0) });
140+
self.rb.cfgr2().modify(|_, w| unsafe { w.ckmode().bits(0) });
141141
self.rb
142-
.ccr
142+
.ccr()
143143
.modify(|_, w| unsafe { w.presc().bits(div as u8) });
144144
}
145145
}
@@ -152,8 +152,8 @@ impl Adc {
152152
///
153153
/// Do not call if an ADC reading is ongoing.
154154
pub fn calibrate(&mut self) {
155-
self.rb.cr.modify(|_, w| w.adcal().set_bit());
156-
while self.rb.cr.read().adcal().bit_is_set() {}
155+
self.rb.cr().modify(|_, w| w.adcal().set_bit());
156+
while self.rb.cr().read().adcal().bit_is_set() {}
157157
}
158158

159159
/// Returns the calibration factors used by the ADC
@@ -166,7 +166,7 @@ impl Adc {
166166
/// Note that VDDA changes and to a lesser extent temperature changes affect the ADC operating conditions and
167167
/// calibration should be run again for the best accuracy.
168168
pub fn get_calibration(&self) -> CalibrationFactor {
169-
CalibrationFactor(self.rb.calfact.read().calfact().bits())
169+
CalibrationFactor(self.rb.calfact().read().calfact().bits())
170170
}
171171

172172
/// Writes the calibration factors used by the ADC
@@ -176,7 +176,7 @@ impl Adc {
176176
/// Do not call if an ADC reading is ongoing.
177177
pub fn set_calibration(&mut self, calfact: CalibrationFactor) {
178178
self.rb
179-
.calfact
179+
.calfact()
180180
.write(|w| unsafe { w.calfact().bits(calfact.0) });
181181
}
182182

@@ -198,34 +198,34 @@ impl Adc {
198198
/// The nuber of bits, the oversampling result is shifted in bits at the end of oversampling
199199
pub fn set_oversampling_shift(&mut self, nrbits: u8) {
200200
self.rb
201-
.cfgr2
201+
.cfgr2()
202202
.modify(|_, w| unsafe { w.ovss().bits(nrbits) });
203203
}
204204

205205
/// Oversampling of adc
206206
pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
207207
self.rb
208-
.cfgr2
208+
.cfgr2()
209209
.modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
210210
}
211211

212212
pub fn oversampling_enable(&mut self, enable: bool) {
213-
self.rb.cfgr2.modify(|_, w| w.ovse().bit(enable));
213+
self.rb.cfgr2().modify(|_, w| w.ovse().bit(enable));
214214
}
215215

216216
pub fn start_injected(&mut self) {
217-
self.rb.cr.modify(|_, w| w.adstart().set_bit());
217+
self.rb.cr().modify(|_, w| w.adstart().set_bit());
218218
// ADSTART bit is cleared to 0 bevor using this function
219219
// enable self.rb.isr.eos() flag is set after each converstion
220-
self.rb.ier.modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
220+
self.rb.ier().modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
221221
}
222222

223223
pub fn stop_injected(&mut self) {
224224
// ?????? or is it reset after each conversion?
225225
// ADSTART bit is cleared to 0 bevor using this function
226226
// disable EOS interrupt
227-
// maybe self.rb.cr.adstp().set_bit() must be performed before interrupt is disabled + wait abortion
228-
self.rb.ier.modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
227+
// maybe self.rb.cr().adstp().set_bit() must be performed before interrupt is disabled + wait abortion
228+
self.rb.ier().modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
229229
}
230230

231231
pub fn read_voltage<PIN: Channel<Adc, ID = u8>>(
@@ -263,15 +263,15 @@ impl Adc {
263263
}
264264

265265
fn power_up(&mut self) {
266-
self.rb.isr.modify(|_, w| w.adrdy().set_bit());
267-
self.rb.cr.modify(|_, w| w.aden().set_bit());
268-
while self.rb.isr.read().adrdy().bit_is_clear() {}
266+
self.rb.isr().modify(|_, w| w.adrdy().set_bit());
267+
self.rb.cr().modify(|_, w| w.aden().set_bit());
268+
while self.rb.isr().read().adrdy().bit_is_clear() {}
269269
}
270270

271271
fn power_down(&mut self) {
272-
self.rb.cr.modify(|_, w| w.addis().set_bit());
273-
self.rb.isr.modify(|_, w| w.adrdy().set_bit());
274-
while self.rb.cr.read().aden().bit_is_set() {}
272+
self.rb.cr().modify(|_, w| w.addis().set_bit());
273+
self.rb.isr().modify(|_, w| w.adrdy().set_bit());
274+
while self.rb.cr().read().aden().bit_is_set() {}
275275
}
276276
}
277277

@@ -300,10 +300,10 @@ where
300300

301301
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
302302
self.rb
303-
.cfgr1
303+
.cfgr1()
304304
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });
305305

306-
self.rb.cfgr1.modify(|_, w| unsafe {
306+
self.rb.cfgr1().modify(|_, w| unsafe {
307307
w.res() // set ADC resolution bits (ADEN must be =0)
308308
.bits(self.precision as u8)
309309
.align() // set alignment bit is (ADSTART must be 0)
@@ -313,7 +313,7 @@ where
313313
self.power_up();
314314

315315
self.rb
316-
.smpr // set sampling time set 1 (ADSTART must be 0)
316+
.smpr() // set sampling time set 1 (ADSTART must be 0)
317317
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
318318

319319
todo!();
@@ -335,17 +335,17 @@ impl DmaMode<Adc> for Adc {
335335

336336
fn dma_enable(&mut self, enable: bool) {
337337
if enable {
338-
self.rb.cfgr1.modify(|_, w| w.dmaen().set_bit()); // enable dma beeing called
338+
self.rb.cfgr1().modify(|_, w| w.dmaen().set_bit()); // enable dma beeing called
339339
} else {
340-
self.rb.cfgr1.modify(|_, w| w.dmaen().clear_bit()); // disable dma beeing called
340+
self.rb.cfgr1().modify(|_, w| w.dmaen().clear_bit()); // disable dma beeing called
341341
}
342342
}
343343

344344
fn dma_circualr_mode(&mut self, enable: bool) {
345345
if enable {
346-
self.rb.cfgr1.modify(|_, w| w.dmacfg().set_bit()); // activate circular mode
346+
self.rb.cfgr1().modify(|_, w| w.dmacfg().set_bit()); // activate circular mode
347347
} else {
348-
self.rb.cfgr1.modify(|_, w| w.dmacfg().clear_bit()); // disable circular mode
348+
self.rb.cfgr1().modify(|_, w| w.dmacfg().clear_bit()); // disable circular mode
349349
}
350350
}
351351
}
@@ -359,26 +359,26 @@ where
359359

360360
fn read(&mut self, _pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
361361
self.power_up();
362-
self.rb.cfgr1.modify(|_, w| unsafe {
362+
self.rb.cfgr1().modify(|_, w| unsafe {
363363
w.res()
364364
.bits(self.precision as u8)
365365
.align()
366366
.bit(self.align == Align::Left)
367367
});
368368

369369
self.rb
370-
.smpr
370+
.smpr()
371371
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
372372

373373
self.rb
374374
.chselr0()
375375
.modify(|_, w| unsafe { w.bits(1 << PIN::channel()) });
376376

377-
self.rb.isr.modify(|_, w| w.eos().set_bit());
378-
self.rb.cr.modify(|_, w| w.adstart().set_bit());
379-
while self.rb.isr.read().eos().bit_is_clear() {}
377+
self.rb.isr().modify(|_, w| w.eos().set_bit());
378+
self.rb.cr().modify(|_, w| w.adstart().set_bit());
379+
while self.rb.isr().read().eos().bit_is_clear() {}
380380

381-
let res = self.rb.dr.read().bits() as u16;
381+
let res = self.rb.dr().read().bits() as u16;
382382
let val = if self.align == Align::Left && self.precision == Precision::B_6 {
383383
res << 8
384384
} else {
@@ -401,15 +401,15 @@ macro_rules! int_adc {
401401
}
402402

403403
pub fn enable(&mut self, adc: &mut Adc) {
404-
adc.rb.ccr.modify(|_, w| w.$en().set_bit());
404+
adc.rb.ccr().modify(|_, w| w.$en().set_bit());
405405
}
406406

407407
pub fn disable(&mut self, adc: &mut Adc) {
408-
adc.rb.ccr.modify(|_, w| w.$en().clear_bit());
408+
adc.rb.ccr().modify(|_, w| w.$en().clear_bit());
409409
}
410410

411411
pub fn enabled(&self, adc: &Adc) -> bool {
412-
adc.rb.ccr.read().$en().bit_is_set()
412+
adc.rb.ccr().read().$en().bit_is_set()
413413
}
414414
}
415415

‎src/crc.rs‎

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@
1919
use crate::rcc::{Enable, Rcc, Reset};
2020
use crate::stm32::CRC;
2121
use core::hash::Hasher;
22-
use core::{cell, ptr};
2322

2423
/// Extension trait to constrain the CRC peripheral.
2524
pub trait CrcExt {
@@ -119,9 +118,9 @@ impl Config {
119118
Some(BitReversal::ByWord) => 0b11,
120119
};
121120

122-
crc.init.write(|w| unsafe { w.crc_init().bits(init) });
123-
crc.pol.write(|w| unsafe { w.bits(poly) });
124-
crc.cr.write(|w| unsafe {
121+
crc.init().write(|w| unsafe { w.crc_init().bits(init) });
122+
crc.pol().write(|w| unsafe { w.bits(poly) });
123+
crc.cr().write(|w| unsafe {
125124
w.rev_in()
126125
.bits(in_rev_bits)
127126
.polysize()
@@ -149,7 +148,7 @@ impl Crc {
149148
pub fn reset(&mut self) {
150149
let crc = unsafe { &(*CRC::ptr()) };
151150

152-
crc.cr.modify(|_, w| w.reset().set_bit());
151+
crc.cr().modify(|_, w| w.reset().set_bit());
153152
}
154153

155154
/// This will reset the CRC to its initial condition, however with a specific initial value.
@@ -160,9 +159,9 @@ impl Crc {
160159
pub fn reset_with_inital_value(&mut self, initial_value: u32) {
161160
let crc = unsafe { &(*CRC::ptr()) };
162161

163-
crc.init
162+
crc.init()
164163
.write(|w| unsafe { w.crc_init().bits(initial_value) });
165-
crc.cr.modify(|_, w| w.reset().set_bit());
164+
crc.cr().modify(|_, w| w.reset().set_bit());
166165
}
167166

168167
/// Feed the CRC with data
@@ -171,7 +170,7 @@ impl Crc {
171170
let crc = unsafe { &(*CRC::ptr()) };
172171
for byte in data {
173172
unsafe {
174-
ptr::write_volatile(cell::UnsafeCell::raw_get(&crc.dr as *const _ as _), byte)
173+
crc.dr().write(|w| w.bits(*byte as _));
175174
}
176175
}
177176
}
@@ -193,7 +192,7 @@ impl Crc {
193192
pub fn peek_result(&self) -> u32 {
194193
let crc = unsafe { &(*CRC::ptr()) };
195194

196-
crc.dr.read().bits()
195+
crc.dr().read().bits()
197196
}
198197
}
199198

‎src/exti.rs‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -68,21 +68,21 @@ impl ExtiExt for EXTI {
6868
let mask = 1 << line;
6969
match edge {
7070
SignalEdge::Rising => {
71-
self.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
71+
self.rtsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
7272
}
7373
SignalEdge::Falling => {
74-
self.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
74+
self.ftsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
7575
}
7676
SignalEdge::All => {
77-
self.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
78-
self.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
77+
self.rtsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
78+
self.ftsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
7979
}
8080
}
8181
self.wakeup(ev);
8282
}
8383

8484
fn wakeup(&self, ev: Event) {
85-
self.imr1
85+
self.imr1()
8686
.modify(|r, w| unsafe { w.bits(r.bits() | 1 << ev as u8) });
8787
}
8888

@@ -91,10 +91,10 @@ impl ExtiExt for EXTI {
9191

9292
let line = ev as u8;
9393
let mask = !(1 << line);
94-
self.imr1.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
94+
self.imr1().modify(|r, w| unsafe { w.bits(r.bits() & mask) });
9595
if line <= TRIGGER_MAX {
96-
self.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
97-
self.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
96+
self.rtsr1().modify(|r, w| unsafe { w.bits(r.bits() & mask) });
97+
self.ftsr1().modify(|r, w| unsafe { w.bits(r.bits() & mask) });
9898
}
9999
}
100100

@@ -105,19 +105,19 @@ impl ExtiExt for EXTI {
105105
}
106106
let mask = 1 << line;
107107
match edge {
108-
SignalEdge::Rising => self.rpr1.read().bits() & mask != 0,
109-
SignalEdge::Falling => self.fpr1.read().bits() & mask != 0,
108+
SignalEdge::Rising => self.rpr1().read().bits() & mask != 0,
109+
SignalEdge::Falling => self.fpr1().read().bits() & mask != 0,
110110
SignalEdge::All => {
111-
(self.rpr1.read().bits() & mask != 0) && (self.fpr1.read().bits() & mask != 0)
111+
(self.rpr1().read().bits() & mask != 0) && (self.fpr1().read().bits() & mask != 0)
112112
}
113113
}
114114
}
115115

116116
fn unpend(&self, ev: Event) {
117117
let line = ev as u8;
118118
if line <= TRIGGER_MAX {
119-
self.rpr1.modify(|_, w| unsafe { w.bits(1 << line) });
120-
self.fpr1.modify(|_, w| unsafe { w.bits(1 << line) });
119+
self.rpr1().modify(|_, w| unsafe { w.bits(1 << line) });
120+
self.fpr1().modify(|_, w| unsafe { w.bits(1 << line) });
121121
}
122122
}
123123
}

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