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update stm32c0 version
1 parent 55ada63 commit accf827

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9 files changed

+26
-21
lines changed

9 files changed

+26
-21
lines changed

‎src/analog/adc.rs‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -132,9 +132,12 @@ impl Adc {
132132
/// Sets ADC source
133133
pub fn set_clock_source(&mut self, clock_source: ClockSource) {
134134
match clock_source {
135-
ClockSource::Pclk(div) => self.rb.cfgr2.modify(|_, w| w.ckmode().bits(div as u8)),
135+
ClockSource::Pclk(div) => self
136+
.rb
137+
.cfgr2
138+
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) }),
136139
ClockSource::Async(div) => {
137-
self.rb.cfgr2.modify(|_, w| w.ckmode().bits(0));
140+
self.rb.cfgr2.modify(|_, w| unsafe { w.ckmode().bits(0) });
138141
self.rb
139142
.ccr
140143
.modify(|_, w| unsafe { w.presc().bits(div as u8) });
@@ -201,7 +204,9 @@ impl Adc {
201204

202205
/// Oversampling of adc
203206
pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
204-
self.rb.cfgr2.modify(|_, w| w.ovsr().bits(ratio as u8));
207+
self.rb
208+
.cfgr2
209+
.modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
205210
}
206211

207212
pub fn oversampling_enable(&mut self, enable: bool) {
@@ -301,9 +306,9 @@ where
301306
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
302307
self.rb
303308
.cfgr1
304-
.modify(|_, w| w.exten().bits(1).extsel().bits(triger_source as u8));
309+
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });
305310

306-
self.rb.cfgr1.modify(|_, w| {
311+
self.rb.cfgr1.modify(|_, w| unsafe {
307312
w.res() // set ADC resolution bits (ADEN must be =0)
308313
.bits(self.precision as u8)
309314
.align() // set alignment bit is (ADSTART must be 0)
@@ -314,7 +319,7 @@ where
314319

315320
self.rb
316321
.smpr // set sampling time set 1 (ADSTART must be 0)
317-
.modify(|_, w| w.smp1().bits(self.sample_time as u8));
322+
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
318323

319324
todo!();
320325
// self.rb
@@ -359,7 +364,7 @@ where
359364

360365
fn read(&mut self, _pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
361366
self.power_up();
362-
self.rb.cfgr1.modify(|_, w| {
367+
self.rb.cfgr1.modify(|_, w| unsafe {
363368
w.res()
364369
.bits(self.precision as u8)
365370
.align()
@@ -368,7 +373,7 @@ where
368373

369374
self.rb
370375
.smpr
371-
.modify(|_, w| w.smp1().bits(self.sample_time as u8));
376+
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
372377

373378
self.rb
374379
.chselr0()

‎src/crc.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ impl Config {
121121

122122
crc.init.write(|w| unsafe { w.crc_init().bits(init) });
123123
crc.pol.write(|w| unsafe { w.bits(poly) });
124-
crc.cr.write(|w| {
124+
crc.cr.write(|w| unsafe {
125125
w.rev_in()
126126
.bits(in_rev_bits)
127127
.polysize()

‎src/rcc/mod.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ impl Rcc {
9191
Prescaler::Div128 => (HSI_FREQ / 128, 0b111),
9292
_ => (HSI_FREQ, 0b000),
9393
};
94-
self.cr.write(|w| w.hsidiv().bits(div_bits));
94+
self.cr.write(|w| unsafe { w.hsidiv().bits(div_bits) });
9595
(freq.Hz(), 0b000)
9696
}
9797
};
@@ -177,7 +177,7 @@ impl Rcc {
177177
RTCSrc::HSE | RTCSrc::HSE_BYPASS => 0b11,
178178
};
179179

180-
self.csr1.modify(|_, w| {
180+
self.csr1.modify(|_, w| unsafe {
181181
w.rtcsel()
182182
.bits(rtc_sel)
183183
.rtcen()

‎src/serial/usart.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -399,7 +399,7 @@ macro_rules! uart {
399399
usart.cr2.reset();
400400
usart.cr3.reset();
401401

402-
usart.cr2.write(|w| {
402+
usart.cr2.write(|w| unsafe {
403403
w.stop()
404404
.bits(config.stopbits.bits())
405405
.swap()

‎src/spi.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -162,14 +162,14 @@ macro_rules! spi {
162162
_ => 0b111,
163163
};
164164

165-
spi.cr2.write(|w| {
165+
spi.cr2.write(|w| unsafe {
166166
w.frxth().set_bit().ds().bits(0b111).ssoe().clear_bit()
167167
});
168168

169169
// Enable pins
170170
pins.setup();
171171

172-
spi.cr1.write(|w| {
172+
spi.cr1.write(|w| unsafe {
173173
w.cpha()
174174
.bit(mode.phase == Phase::CaptureOnSecondTransition)
175175
.cpol()
@@ -198,7 +198,7 @@ macro_rules! spi {
198198
}
199199

200200
pub fn data_size(&mut self, nr_bits: u8) {
201-
self.spi.cr2.modify(|_, w| {
201+
self.spi.cr2.modify(|_, w| unsafe {
202202
w.ds().bits(nr_bits-1)
203203
});
204204
}

‎src/timer/mod.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -238,13 +238,13 @@ macro_rules! timers_external_clocks {
238238
self.clk = freq;
239239
match clk.mode() {
240240
ExternalClockMode::Mode1 => {
241-
self.tim.smcr.modify(|_, w| w.$sms().bits(0b111));
241+
self.tim.smcr.modify(|_, w| unsafe { w.$sms().bits(0b111) });
242242
$(
243243
self.tim.smcr.modify(|_, w| w.$ece().clear_bit());
244244
)*
245245
},
246246
ExternalClockMode::Mode2 => {
247-
self.tim.smcr.modify(|_, w| w.$sms().bits(0b0));
247+
self.tim.smcr.modify(|_, w| unsafe { w.$sms().bits(0b0) });
248248
$(
249249
self.tim.smcr.modify(|_, w| w.$ece().set_bit());
250250
)*

‎src/timer/pins.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ macro_rules! trigger_pins {
6464
}
6565
};
6666

67-
tim.smcr.modify(|_, w| w.ts1().bits(ts) );
67+
tim.smcr.modify(|_, w| unsafe { w.ts1().bits(ts) });
6868

6969
Self {
7070
pin,

‎src/timer/qei.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,10 +47,10 @@ macro_rules! qei {
4747
$TIMX::reset(rcc);
4848

4949
// Configure TxC1 and TxC2 as captures
50-
tim.ccmr1_output().write(|w| w.cc1s().bits(0b01).cc2s().bits(0b01));
50+
tim.ccmr1_output().write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
5151

5252
// Encoder mode 2.
53-
tim.smcr.write(|w| w.sms1().bits(0b010));
53+
tim.smcr.write(|w| unsafe { w.sms1().bits(0b010) });
5454

5555
// Enable and configure to capture on rising edge
5656
tim.ccer.write(|w| {

‎src/watchdog.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ impl IndependedWatchdog {
3232
// Enable access to RLR/PR
3333
self.iwdg.kr.write(|w| unsafe { w.key().bits(0x5555) });
3434

35-
self.iwdg.pr.write(|w| w.pr().bits(psc));
35+
self.iwdg.pr.write(|w| unsafe { w.pr().bits(psc) });
3636
self.iwdg
3737
.rlr
3838
.write(|w| unsafe { w.rl().bits(reload as u16) });

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