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Merge pull request #4 from starboundstitch/starboundstitch/fix-compile
Fix compiling errors following by update a peripheral repo.
2 parents d96233a + 28d003f commit e03b5b5

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9 files changed

+117
-130
lines changed

9 files changed

+117
-130
lines changed

‎src/analog/adc.rs‎

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ impl Adc {
118118
// Enable ADC clocks
119119
ADC::enable(rcc);
120120

121-
adc.cr().modify(|_, w| w.advregen().set_bit());
121+
adc.cr().modify(|_, w| w.advregen().bit(true));
122122

123123
Self {
124124
rb: adc,
@@ -132,10 +132,12 @@ impl Adc {
132132
/// Sets ADC source
133133
pub fn set_clock_source(&mut self, clock_source: ClockSource) {
134134
match clock_source {
135-
ClockSource::Pclk(div) => self
136-
.rb
137-
.cfgr2()
138-
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) }),
135+
ClockSource::Pclk(div) => {
136+
_ = self
137+
.rb
138+
.cfgr2()
139+
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) })
140+
}
139141
ClockSource::Async(div) => {
140142
self.rb.cfgr2().modify(|_, w| unsafe { w.ckmode().bits(0) });
141143
self.rb
@@ -152,7 +154,7 @@ impl Adc {
152154
///
153155
/// Do not call if an ADC reading is ongoing.
154156
pub fn calibrate(&mut self) {
155-
self.rb.cr().modify(|_, w| w.adcal().set_bit());
157+
self.rb.cr().modify(|_, w| w.adcal().bit(true));
156158
while self.rb.cr().read().adcal().bit_is_set() {}
157159
}
158160

@@ -214,10 +216,10 @@ impl Adc {
214216
}
215217

216218
pub fn start_injected(&mut self) {
217-
self.rb.cr().modify(|_, w| w.adstart().set_bit());
219+
self.rb.cr().modify(|_, w| w.adstart().bit(true));
218220
// ADSTART bit is cleared to 0 bevor using this function
219221
// enable self.rb.isr.eos() flag is set after each converstion
220-
self.rb.ier().modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
222+
self.rb.ier().modify(|_, w| w.eocie().bit(true)); // end of sequence interupt enable
221223
}
222224

223225
pub fn stop_injected(&mut self) {
@@ -263,14 +265,14 @@ impl Adc {
263265
}
264266

265267
fn power_up(&mut self) {
266-
self.rb.isr().modify(|_, w| w.adrdy().set_bit());
268+
self.rb.isr().modify(|_, w| w.adrdy().bit(true));
267269
self.rb.cr().modify(|_, w| w.aden().set_bit());
268270
while self.rb.isr().read().adrdy().bit_is_clear() {}
269271
}
270272

271273
fn power_down(&mut self) {
272274
self.rb.cr().modify(|_, w| w.addis().set_bit());
273-
self.rb.isr().modify(|_, w| w.adrdy().set_bit());
275+
self.rb.isr().modify(|_, w| w.adrdy().bit(true));
274276
while self.rb.cr().read().aden().bit_is_set() {}
275277
}
276278
}
@@ -374,7 +376,7 @@ where
374376
.chselr0()
375377
.modify(|_, w| unsafe { w.bits(1 << PIN::channel()) });
376378

377-
self.rb.isr().modify(|_, w| w.eos().set_bit());
379+
self.rb.isr().modify(|_, w| w.eos().bit(true));
378380
self.rb.cr().modify(|_, w| w.adstart().set_bit());
379381
while self.rb.isr().read().eos().bit_is_clear() {}
380382

‎src/gpio.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -75,12 +75,12 @@ macro_rules! gpio_trait {
7575

7676
fn set_high(&self, pos: u8) {
7777
// NOTE(unsafe) atomic write to a stateless register
78-
unsafe { self.bsrr().write(|w| w.bits(1 << pos)) }
78+
unsafe { self.bsrr().write(|w| w.bits(1 << pos)) };
7979
}
8080

8181
fn set_low(&self, pos: u8) {
8282
// NOTE(unsafe) atomic write to a stateless register
83-
unsafe { self.bsrr().write(|w| w.bits(1 << (pos + 16))) }
83+
unsafe { self.bsrr().write(|w| w.bits(1 << (pos + 16))) };
8484
}
8585
}
8686
};
@@ -474,7 +474,7 @@ macro_rules! gpio {
474474
w.bits(r.bits() & reset | mask)
475475
}),
476476
_ => unreachable!(),
477-
}
477+
};
478478
exti.listen(Event::from_code($i), edge);
479479
$PXi { _mode: PhantomData }
480480
}

‎src/i2c/blocking.rs‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ use crate::gpio::*;
33
use crate::i2c::config::Config;
44
use crate::i2c::{self, Error, I2c, I2cDirection, I2cExt, SCLPin, SDAPin};
55
use crate::rcc::*;
6-
use crate::stm32::I2C;
6+
use crate::stm32::I2C1;
77
use hal::blocking::i2c::{Read, Write, WriteRead};
88

99
pub trait I2cSlave {
@@ -42,7 +42,7 @@ macro_rules! flush_txdr {
4242

4343
// If TXDR is not flagged as empty, write 1 to flush it
4444
if $i2c.isr().read().txe().bit_is_set() {
45-
$i2c.isr().write(|w| w.txe().set_bit());
45+
$i2c.isr().write(|w| w.txe().bit(true));
4646
}
4747
};
4848
}
@@ -67,19 +67,19 @@ macro_rules! busy_wait {
6767
if isr.$flag().$variant() {
6868
break
6969
} else if isr.berr().bit_is_set() {
70-
$i2c.icr().write(|w| w.berrcf().set_bit());
70+
$i2c.icr().write(|w| w.berrcf().bit(true));
7171
return Err(Error::BusError);
7272
} else if isr.arlo().bit_is_set() {
73-
$i2c.icr().write(|w| w.arlocf().set_bit());
73+
$i2c.icr().write(|w| w.arlocf().bit(true));
7474
return Err(Error::ArbitrationLost);
7575
} else if isr.nackf().bit_is_set() {
76-
$i2c.icr().write(|w| w.nackcf().set_bit());
76+
$i2c.icr().write(|w| w.nackcf().bit(true));
7777
// Make one extra loop to wait on the stop condition
7878
} else if isr.tcr().bit_is_set() {
7979
// This condition Will only happen when reload == 1 and sbr == 1 (slave) and nbytes was written.
8080
// Send a NACK, set nbytes to clear tcr flag
8181
$i2c.cr2().modify(|_, w| unsafe {
82-
w.nack().set_bit().nbytes().bits(1 as u8)
82+
w.nack().bit(true).nbytes().bits(1 as u8)
8383
});
8484
// Make one extra loop here to wait on the stop condition
8585
} else if isr.addr().bit_is_set() {
@@ -93,7 +93,7 @@ macro_rules! busy_wait {
9393
} else if isr.stopf().bit_is_set() {
9494
flush_txdr!($i2c);
9595
// Clear the stop condition flag
96-
$i2c.icr().write(|w| w.stopcf().set_bit());
96+
$i2c.icr().write(|w| w.stopcf().bit(true));
9797
if $idx == $buflen {
9898
return Ok( () )
9999
} else
@@ -178,7 +178,7 @@ macro_rules! i2c {
178178
// Enable the I2C processing
179179
i2c.cr1().modify(|_, w| unsafe {
180180
w.pe()
181-
.set_bit()
181+
.bit(true)
182182
.dnf()
183183
.bits(config.digital_filter)
184184
.anfoff()
@@ -189,20 +189,20 @@ macro_rules! i2c {
189189
i2c.oar1().write(|w| unsafe {
190190
w.oa1().bits(config.slave_address_1)
191191
.oa1mode().bit(config.address_11bits)
192-
.oa1en().set_bit()
192+
.oa1en().bit(true)
193193
});
194194
// Enable acknowlidge control
195-
i2c.cr1().modify(|_, w| w.sbc().set_bit() );
195+
i2c.cr1().modify(|_, w| w.sbc().bit(true) );
196196
}
197197

198198
if config.slave_address_2 > 0 {
199199
i2c.oar2().write( |w| unsafe {
200200
w.oa2msk().bits( config.slave_address_mask as u8)
201201
.oa2().bits(config.slave_address_2)
202-
.oa2en().set_bit()
202+
.oa2en().bit(true)
203203
});
204204
// Enable acknowlidge control
205-
i2c.cr1().modify(|_, w| w.sbc().set_bit() );
205+
i2c.cr1().modify(|_, w| w.sbc().bit(true) );
206206
}
207207

208208
// Enable pins
@@ -214,21 +214,21 @@ macro_rules! i2c {
214214

215215
pub fn listen(&mut self, ev: i2c::Event) {
216216
match ev {
217-
i2c::Event::AddressMatch => self.i2c.cr1().modify(|_, w| w.addrie().set_bit()),
218-
i2c::Event::Rxne => self.i2c.cr1().modify(|_, w| w.rxie().set_bit()),
219-
}
217+
i2c::Event::AddressMatch => self.i2c.cr1().modify(|_, w| w.addrie().bit(true)),
218+
i2c::Event::Rxne => self.i2c.cr1().modify(|_, w| w.rxie().bit(true)),
219+
};
220220
}
221221

222222
pub fn unlisten(&mut self, ev: i2c::Event) {
223223
match ev {
224224
i2c::Event::AddressMatch => self.i2c.cr1().modify(|_, w| w.addrie().clear_bit()),
225225
i2c::Event::Rxne => self.i2c.cr1().modify(|_, w| w.rxie().clear_bit()),
226-
}
226+
};
227227
}
228228

229229
pub fn clear_irq(&mut self, ev: i2c::Event) {
230230
match ev {
231-
i2c::Event::AddressMatch => self.i2c.icr().write(|w| w.addrcf().set_bit()),
231+
i2c::Event::AddressMatch => _ = self.i2c.icr().write(|w| w.addrcf().bit(true)),
232232
_ => {},
233233
}
234234
}
@@ -257,7 +257,7 @@ macro_rules! i2c {
257257
while self.i2c.cr2().read().start().bit_is_set() {};
258258

259259
// flush i2c tx register
260-
self.i2c.isr().write(|w| w.txe().set_bit());
260+
self.i2c.isr().write(|w| w.txe().bit(true));
261261

262262
// Set START and prepare to send `bytes`.
263263
// The START bit can be set even if the bus is BUSY or
@@ -276,7 +276,7 @@ macro_rules! i2c {
276276
.autoend().clear_bit()
277277
.reload().clear_bit()
278278
// Start transfer
279-
.start().set_bit()
279+
.start().bit(true)
280280
});
281281
let mut idx = 0;
282282
// Wait until we are allowed to send data
@@ -302,12 +302,12 @@ macro_rules! i2c {
302302
// 7-bit addressing mode
303303
.add10().clear_bit()
304304
// Set transfer direction to read
305-
.rd_wrn().set_bit()
305+
.rd_wrn().bit(true)
306306
// Automatic end mode
307-
.autoend().set_bit()
307+
.autoend().bit(true)
308308
.reload().clear_bit()
309309
// Start transfer
310-
.start().set_bit()
310+
.start().bit(true)
311311
});
312312

313313
idx = 0;
@@ -336,15 +336,15 @@ macro_rules! i2c {
336336
self.i2c.cr2().modify(|_, w| unsafe {
337337
w
338338
// Start transfer
339-
.start().set_bit()
339+
.start().bit(true)
340340
// Set number of bytes to transfer
341341
.nbytes().bits(buflen as u8)
342342
// Set address to transfer to/from
343343
.sadd().bits((addr << 1) as u16)
344344
// Set transfer direction to write
345345
.rd_wrn().clear_bit()
346346
// Automatic end mode
347-
.autoend().set_bit()
347+
.autoend().bit(true)
348348
.reload().clear_bit()
349349
});
350350

@@ -381,15 +381,15 @@ macro_rules! i2c {
381381
self.i2c.cr2().modify(|_, w| unsafe {
382382
w
383383
// Start transfer
384-
.start().set_bit()
384+
.start().bit(true)
385385
// Set number of bytes to transfer
386386
.nbytes().bits(buflen as u8)
387387
// Set address to transfer to/from
388388
.sadd().bits((addr << 1) as u16)
389389
// Set transfer direction to read
390-
.rd_wrn().set_bit()
390+
.rd_wrn().bit(true)
391391
// automatic end mode
392-
.autoend().set_bit()
392+
.autoend().bit(true)
393393
.reload().clear_bit()
394394
});
395395
let mut idx = 0;
@@ -449,9 +449,9 @@ macro_rules! i2c {
449449
.reload().clear_bit()
450450
});
451451
// flush i2c tx register
452-
self.i2c.isr().write(|w| w.txe().set_bit());
452+
self.i2c.isr().write(|w| w.txe().bit(true));
453453
// end address phase, release clock stretching
454-
self.i2c.icr().write(|w| w.addrcf().set_bit() );
454+
self.i2c.icr().write(|w| w.addrcf().bit(true) );
455455

456456
let mut idx = 0;
457457
loop {
@@ -481,11 +481,11 @@ macro_rules! i2c {
481481
// Set number of bytes to transfer: maximum as all incoming bytes will be ACK'ed
482482
.nbytes().bits(buflen as u8)
483483
// during sending nbytes automatically send a ACK, stretch clock after last byte
484-
.reload().set_bit()
484+
.reload().bit(true)
485485
});
486486
// end address phase, release clock stretching
487487
self.i2c.icr().write(|w|
488-
w.addrcf().set_bit()
488+
w.addrcf().bit(true)
489489
);
490490
flush_rxdr!(self.i2c);
491491

@@ -506,7 +506,7 @@ macro_rules! i2c {
506506
}
507507

508508
i2c!(
509-
I2C,
509+
I2C1,
510510
i2c1,
511511
sda: [
512512
(PA10<Output<OpenDrain>>, AltFunction::AF6),

‎src/power.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -55,11 +55,11 @@ impl Power {
5555

5656
pub fn clear_wakeup_flag<L: Into<WakeUp>>(&mut self, lane: L) {
5757
match lane.into() {
58-
WakeUp::Line1 => self.rb.scr().write(|w| w.cwuf1().set_bit()),
59-
WakeUp::Line2 => self.rb.scr().write(|w| w.cwuf2().set_bit()),
60-
WakeUp::Line3 => self.rb.scr().write(|w| w.cwuf3().set_bit()),
61-
WakeUp::Line4 => self.rb.scr().write(|w| w.cwuf4().set_bit()),
62-
WakeUp::Line6 => self.rb.scr().write(|w| w.cwuf6().set_bit()),
58+
WakeUp::Line1 => _ = self.rb.scr().write(|w| w.cwuf1().set_bit()),
59+
WakeUp::Line2 => _ = self.rb.scr().write(|w| w.cwuf2().set_bit()),
60+
WakeUp::Line3 => _ = self.rb.scr().write(|w| w.cwuf3().set_bit()),
61+
WakeUp::Line4 => _ = self.rb.scr().write(|w| w.cwuf4().set_bit()),
62+
WakeUp::Line6 => _ = self.rb.scr().write(|w| w.cwuf6().set_bit()),
6363
_ => {}
6464
}
6565
}
@@ -93,7 +93,7 @@ impl Power {
9393
self.rb.cr3().modify(|_, w| w.ewup6().set_bit());
9494
self.rb.cr4().modify(|_, w| w.wp6().bit(edge));
9595
}
96-
WakeUp::InternalLine => self.rb.cr3().modify(|_, w| w.eiwul().set_bit()),
96+
WakeUp::InternalLine => _ = self.rb.cr3().modify(|_, w| w.eiwul().set_bit()),
9797
}
9898
}
9999

@@ -105,7 +105,7 @@ impl Power {
105105
WakeUp::Line4 => self.rb.cr3().modify(|_, w| w.ewup4().clear_bit()),
106106
WakeUp::Line6 => self.rb.cr3().modify(|_, w| w.ewup6().clear_bit()),
107107
WakeUp::InternalLine => self.rb.cr3().modify(|_, w| w.eiwul().clear_bit()),
108-
}
108+
};
109109
}
110110

111111
pub fn set_mode(&mut self, _mode: PowerMode) {

‎src/rcc/enable.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,10 +115,10 @@ bus! {
115115
DMA => (AHB, dma1en, dma1smen, dma1rst), // 0
116116

117117
DBG => (APB1, dbgen, dbgsmen, dbgrst), // 27
118-
I2C => (APB1, i2c1en, i2c1smen, i2c1rst), // 21
118+
I2C1 => (APB1, i2c1en, i2c1smen, i2c1rst), // 21
119119
PWR => (APB1, pwren, pwrsmen, pwrrst), // 28
120120

121-
SPI => (APB2, spi1en, spi1smen, spi1rst), // 14
121+
SPI1 => (APB2, spi1en, spi1smen, spi1rst), // 14
122122
TIM3 => (APB1, tim3en, tim3smen, tim3rst), // 1
123123
USART2 => (APB1, usart2en, usart2smen, usart2rst), // 17
124124
WWDG => (APB1, wwdgen, wwdgsmen,), // 11

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