From f3744fe19b31adee1069e62af317d32e68de5cc5 Mon Sep 17 00:00:00 2001
From: Dima Pulkinen <dima@itsemast.com>
Date: Mon, 21 Apr 2025 13:37:41 +0300
Subject: [PATCH] fix timer macros and pin configurations for consistency

---
 src/timer/mod.rs  | 4 ++--
 src/timer/pins.rs | 2 +-
 src/timer/qei.rs  | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/timer/mod.rs b/src/timer/mod.rs
index 706efa0..ae490c2 100644
--- a/src/timer/mod.rs
+++ b/src/timer/mod.rs
@@ -257,8 +257,8 @@ macro_rules! timers_external_clocks {
 }
 
 timers_external_clocks! {
-    TIM1: (tim1, sms1, ece),
-    TIM3: (tim3, sms1, ece),
+    TIM1: (tim1, sms, ece),
+    TIM3: (tim3, sms, ece),
 }
 
 timers! {
diff --git a/src/timer/pins.rs b/src/timer/pins.rs
index ac663c5..1ac937a 100644
--- a/src/timer/pins.rs
+++ b/src/timer/pins.rs
@@ -64,7 +64,7 @@ macro_rules! trigger_pins {
                         }
                     };
 
-                    tim.smcr().modify(|_, w| unsafe { w.ts1().bits(ts) });
+                    tim.smcr().modify(|_, w| unsafe { w.ts().bits(ts) });
 
                     Self {
                         pin,
diff --git a/src/timer/qei.rs b/src/timer/qei.rs
index ebc8300..e11e3ba 100644
--- a/src/timer/qei.rs
+++ b/src/timer/qei.rs
@@ -50,7 +50,7 @@ macro_rules! qei {
                     tim.ccmr1_output().write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
 
                     // Encoder mode 2.
-                    tim.smcr().write(|w| unsafe { w.sms1().bits(0b010) });
+                    tim.smcr().write(|w| unsafe { w.sms().bits(0b010) });
 
                     // Enable and configure to capture on rising edge
                     tim.ccer().write(|w| {