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1 parent 02c01cd commit 6a02615Copy full SHA for 6a02615
src/watchdog.rs
@@ -114,8 +114,7 @@ impl watchdog::WatchdogEnable for Watchdog {
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self.iwdg.rlr.write(|w| w.rl().bits(time.reload));
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// Wait until the registers are updated before issuing a reset with
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// (potentially false) values
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- while self.iwdg.sr.read().pvu().bit() {}
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- while self.iwdg.sr.read().rvu().bit() {}
+ while self.iwdg.sr.read().bits() != 0 {}
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self.iwdg.kr.write(|w| w.key().reset());
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}
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