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burrbullburrbull
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fmt spi
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2 files changed

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‎CHANGELOG.md‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1515
- `PwmHz::get_period`: fix computation of return value, prevent division by zero
1616
- return `i2c::Error::Timeout` instead of `nb::WouldBlock` when time is out
1717
- support `embedded-hal-1.0-alpha`
18-
- `gpio`: port and pin generics first, then mode, `PinMode` for modes instead of pins, other cleanups
1918

2019
### Breaking changes
2120

‎src/spi.rs‎

Lines changed: 90 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -490,40 +490,28 @@ where
490490
};
491491

492492
spi.cr1.write(|w| {
493-
w
494-
// clock phase from config
495-
.cpha()
496-
.bit(mode.phase == Phase::CaptureOnSecondTransition)
497-
// clock polarity from config
498-
.cpol()
499-
.bit(mode.polarity == Polarity::IdleHigh)
500-
// mstr: master configuration
501-
.mstr()
502-
.set_bit()
503-
// baudrate value
504-
.br()
505-
.bits(br)
506-
// lsbfirst: MSB first
507-
.lsbfirst()
508-
.clear_bit()
509-
// ssm: enable software slave management (NSS pin free for other uses)
510-
.ssm()
511-
.set_bit()
512-
// ssi: set nss high = master mode
513-
.ssi()
514-
.set_bit()
515-
// dff: 8 bit frames
516-
.dff()
517-
.clear_bit()
518-
// bidimode: 2-line unidirectional
519-
.bidimode()
520-
.clear_bit()
521-
// both TX and RX are used
522-
.rxonly()
523-
.clear_bit()
524-
// spe: enable the SPI bus
525-
.spe()
526-
.set_bit()
493+
// clock phase from config
494+
w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition);
495+
// clock polarity from config
496+
w.cpol().bit(mode.polarity == Polarity::IdleHigh);
497+
// mstr: master configuration
498+
w.mstr().set_bit();
499+
// baudrate value
500+
w.br().bits(br);
501+
// lsbfirst: MSB first
502+
w.lsbfirst().clear_bit();
503+
// ssm: enable software slave management (NSS pin free for other uses)
504+
w.ssm().set_bit();
505+
// ssi: set nss high = master mode
506+
w.ssi().set_bit();
507+
// dff: 8 bit frames
508+
w.dff().clear_bit();
509+
// bidimode: 2-line unidirectional
510+
w.bidimode().clear_bit();
511+
// both TX and RX are used
512+
w.rxonly().clear_bit();
513+
// spe: enable the SPI bus
514+
w.spe().set_bit()
527515
});
528516

529517
Spi {
@@ -550,37 +538,26 @@ where
550538
spi.cr2.write(|w| w.ssoe().clear_bit());
551539

552540
spi.cr1.write(|w| {
553-
w
554-
// clock phase from config
555-
.cpha()
556-
.bit(mode.phase == Phase::CaptureOnSecondTransition)
557-
// clock polarity from config
558-
.cpol()
559-
.bit(mode.polarity == Polarity::IdleHigh)
560-
// mstr: slave configuration
561-
.mstr()
562-
.clear_bit()
563-
// lsbfirst: MSB first
564-
.lsbfirst()
565-
.clear_bit()
566-
// ssm: enable software slave management (NSS pin free for other uses)
567-
.ssm()
568-
.set_bit()
569-
// ssi: set nss low = slave mode
570-
.ssi()
571-
.clear_bit()
572-
// dff: 8 bit frames
573-
.dff()
574-
.clear_bit()
575-
// bidimode: 2-line unidirectional
576-
.bidimode()
577-
.clear_bit()
578-
// both TX and RX are used
579-
.rxonly()
580-
.clear_bit()
581-
// spe: enable the SPI bus
582-
.spe()
583-
.set_bit()
541+
// clock phase from config
542+
w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition);
543+
// clock polarity from config
544+
w.cpol().bit(mode.polarity == Polarity::IdleHigh);
545+
// mstr: slave configuration
546+
w.mstr().clear_bit();
547+
// lsbfirst: MSB first
548+
w.lsbfirst().clear_bit();
549+
// ssm: enable software slave management (NSS pin free for other uses)
550+
w.ssm().set_bit();
551+
// ssi: set nss low = slave mode
552+
w.ssi().clear_bit();
553+
// dff: 8 bit frames
554+
w.dff().clear_bit();
555+
// bidimode: 2-line unidirectional
556+
w.bidimode().clear_bit();
557+
// both TX and RX are used
558+
w.rxonly().clear_bit();
559+
// spe: enable the SPI bus
560+
w.spe().set_bit()
584561
});
585562

586563
Spi {
@@ -772,25 +749,18 @@ macro_rules! spi_dma {
772749

773750
atomic::compiler_fence(Ordering::Release);
774751
self.channel.ch().cr.modify(|_, w| {
775-
w
776-
// memory to memory mode disabled
777-
.mem2mem()
778-
.clear_bit()
779-
// medium channel priority level
780-
.pl()
781-
.medium()
782-
// 8-bit memory size
783-
.msize()
784-
.bits8()
785-
// 8-bit peripheral size
786-
.psize()
787-
.bits8()
788-
// circular mode disabled
789-
.circ()
790-
.clear_bit()
791-
// write to memory
792-
.dir()
793-
.clear_bit()
752+
// memory to memory mode disabled
753+
w.mem2mem().clear_bit();
754+
// medium channel priority level
755+
w.pl().medium();
756+
// 8-bit memory size
757+
w.msize().bits8();
758+
// 8-bit peripheral size
759+
w.psize().bits8();
760+
// circular mode disabled
761+
w.circ().clear_bit();
762+
// write to memory
763+
w.dir().clear_bit()
794764
});
795765
self.start();
796766

@@ -816,25 +786,18 @@ macro_rules! spi_dma {
816786

817787
atomic::compiler_fence(Ordering::Release);
818788
self.channel.ch().cr.modify(|_, w| {
819-
w
820-
// memory to memory mode disabled
821-
.mem2mem()
822-
.clear_bit()
823-
// medium channel priority level
824-
.pl()
825-
.medium()
826-
// 8-bit memory size
827-
.msize()
828-
.bits8()
829-
// 8-bit peripheral size
830-
.psize()
831-
.bits8()
832-
// circular mode disabled
833-
.circ()
834-
.clear_bit()
835-
// read from memory
836-
.dir()
837-
.set_bit()
789+
// memory to memory mode disabled
790+
w.mem2mem().clear_bit();
791+
// medium channel priority level
792+
w.pl().medium();
793+
// 8-bit memory size
794+
w.msize().bits8();
795+
// 8-bit peripheral size
796+
w.psize().bits8();
797+
// circular mode disabled
798+
w.circ().clear_bit();
799+
// read from memory
800+
w.dir().set_bit()
838801
});
839802
self.start();
840803

@@ -878,46 +841,32 @@ macro_rules! spi_dma {
878841

879842
atomic::compiler_fence(Ordering::Release);
880843
self.rxchannel.ch().cr.modify(|_, w| {
881-
w
882-
// memory to memory mode disabled
883-
.mem2mem()
884-
.clear_bit()
885-
// medium channel priority level
886-
.pl()
887-
.medium()
888-
// 8-bit memory size
889-
.msize()
890-
.bits8()
891-
// 8-bit peripheral size
892-
.psize()
893-
.bits8()
894-
// circular mode disabled
895-
.circ()
896-
.clear_bit()
897-
// write to memory
898-
.dir()
899-
.clear_bit()
844+
// memory to memory mode disabled
845+
w.mem2mem().clear_bit();
846+
// medium channel priority level
847+
w.pl().medium();
848+
// 8-bit memory size
849+
w.msize().bits8();
850+
// 8-bit peripheral size
851+
w.psize().bits8();
852+
// circular mode disabled
853+
w.circ().clear_bit();
854+
// write to memory
855+
w.dir().clear_bit()
900856
});
901857
self.txchannel.ch().cr.modify(|_, w| {
902-
w
903-
// memory to memory mode disabled
904-
.mem2mem()
905-
.clear_bit()
906-
// medium channel priority level
907-
.pl()
908-
.medium()
909-
// 8-bit memory size
910-
.msize()
911-
.bits8()
912-
// 8-bit peripheral size
913-
.psize()
914-
.bits8()
915-
// circular mode disabled
916-
.circ()
917-
.clear_bit()
918-
// read from memory
919-
.dir()
920-
.set_bit()
858+
// memory to memory mode disabled
859+
w.mem2mem().clear_bit();
860+
// medium channel priority level
861+
w.pl().medium();
862+
// 8-bit memory size
863+
w.msize().bits8();
864+
// 8-bit peripheral size
865+
w.psize().bits8();
866+
// circular mode disabled
867+
w.circ().clear_bit();
868+
// read from memory
869+
w.dir().set_bit()
921870
});
922871
self.start();
923872

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