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burrbullburrbull
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bump stm32f1
1 parent 0588013 commit 6180620

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11 files changed

+64
-69
lines changed

11 files changed

+64
-69
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‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1919

2020
### Breaking changes
2121

22+
- Bump `stm32f1` dependency (`0.8.0`)
2223
- ADC now requires the clock configuration for intialisation
2324
- `disable_jtag` now transforms PA15, PB3 and PB4 to forbid their use without desactivating JTAG
2425

‎Cargo.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ required-features = ["rt"]
2222
cortex-m = "0.6.0"
2323
nb = "0.1.2"
2424
cortex-m-rt = "0.6.8"
25-
stm32f1 = "0.7.0"
25+
stm32f1 = "0.8.0"
2626

2727
[dependencies.void]
2828
default-features = false

‎src/adc.rs‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -462,13 +462,13 @@ impl Adc<ADC1> {
462462
// so use the following approximate settings
463463
// to support all ADC frequencies
464464
let sample_time = match self.clocks.adcclk().0 {
465-
0 ... 1_200_000 => AdcSampleTime::T_1,
466-
1_200_001 ... 1_500_000 => AdcSampleTime::T_7,
467-
1_500_001 ... 2_400_000 => AdcSampleTime::T_13,
468-
2_400_001 ... 3_100_000 => AdcSampleTime::T_28,
469-
3_100_001 ... 4_000_000 => AdcSampleTime::T_41,
470-
4_000_001 ... 5_000_000 => AdcSampleTime::T_55,
471-
5_000_001 ... 14_000_000 => AdcSampleTime::T_71,
465+
0 ..= 1_200_000 => AdcSampleTime::T_1,
466+
1_200_001 ..= 1_500_000 => AdcSampleTime::T_7,
467+
1_500_001 ..= 2_400_000 => AdcSampleTime::T_13,
468+
2_400_001 ..= 3_100_000 => AdcSampleTime::T_28,
469+
3_100_001 ..= 4_000_000 => AdcSampleTime::T_41,
470+
4_000_001 ..= 5_000_000 => AdcSampleTime::T_55,
471+
5_000_001 ..= 14_000_000 => AdcSampleTime::T_71,
472472
_ => AdcSampleTime::T_239,
473473
};
474474

@@ -598,8 +598,8 @@ where
598598
self.channel.ch().cr.modify(|_, w| { w
599599
.mem2mem() .clear_bit()
600600
.pl() .medium()
601-
.msize() .bit16()
602-
.psize() .bit16()
601+
.msize() .bits16()
602+
.psize() .bits16()
603603
.circ() .set_bit()
604604
.dir() .clear_bit()
605605
});
@@ -627,13 +627,13 @@ where
627627
self.channel.ch().cr.modify(|_, w| { w
628628
.mem2mem() .clear_bit()
629629
.pl() .medium()
630-
.msize() .bit16()
631-
.psize() .bit16()
630+
.msize() .bits16()
631+
.psize() .bits16()
632632
.circ() .clear_bit()
633633
.dir() .clear_bit()
634634
});
635635
self.start();
636636

637637
Transfer::w(buffer, self)
638638
}
639-
}
639+
}

‎src/gpio.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,7 @@ macro_rules! gpio {
199199
/// Put the pin in an active state. The caller
200200
/// must enforce that the pin is really in this
201201
/// state in the hardware.
202+
#[allow(dead_code)]
202203
pub(crate) unsafe fn activate(self) -> $PXi<Input<Floating>> {
203204
$PXi { _mode: PhantomData }
204205
}

‎src/pwm.rs‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -309,33 +309,33 @@ macro_rules! hal {
309309
apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
310310

311311
if PINS::C1 {
312-
tim.ccmr1_output
313-
.modify(|_, w| unsafe { w.oc1pe().set_bit().oc1m().bits(6) });
312+
tim.ccmr1_output()
313+
.modify(|_, w| w.oc1pe().set_bit().oc1m().pwm_mode1() );
314314
}
315315

316316
if PINS::C2 {
317-
tim.ccmr1_output
318-
.modify(|_, w| unsafe { w.oc2pe().set_bit().oc2m().bits(6) });
317+
tim.ccmr1_output()
318+
.modify(|_, w| w.oc2pe().set_bit().oc2m().pwm_mode1() );
319319
}
320320

321321
if PINS::C3 {
322-
tim.ccmr2_output
323-
.modify(|_, w| unsafe { w.oc3pe().set_bit().oc3m().bits(6) });
322+
tim.ccmr2_output()
323+
.modify(|_, w| w.oc3pe().set_bit().oc3m().pwm_mode1() );
324324
}
325325

326326
if PINS::C4 {
327-
tim.ccmr2_output
328-
.modify(|_, w| unsafe { w.oc4pe().set_bit().oc4m().bits(6) });
327+
tim.ccmr2_output()
328+
.modify(|_, w| w.oc4pe().set_bit().oc4m().pwm_mode1() );
329329
}
330330
let clk = $TIMX::get_clk(&clocks).0;
331331
let freq = freq.0;
332332
let ticks = clk / freq;
333333
let psc = u16(ticks / (1 << 16)).unwrap();
334-
tim.psc.write(|w| unsafe { w.psc().bits(psc) });
334+
tim.psc.write(|w| w.psc().bits(psc) );
335335
let arr = u16(ticks / u32(psc + 1)).unwrap();
336-
tim.arr.write(|w| { w.arr().bits(arr) });
336+
tim.arr.write(|w| w.arr().bits(arr));
337337

338-
tim.cr1.write(|w| unsafe {
338+
tim.cr1.write(|w|
339339
w.cms()
340340
.bits(0b00)
341341
.dir()
@@ -344,7 +344,7 @@ macro_rules! hal {
344344
.clear_bit()
345345
.cen()
346346
.set_bit()
347-
});
347+
);
348348

349349
unsafe { mem::uninitialized() }
350350
}

‎src/pwm_input.rs‎

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -211,13 +211,7 @@ macro_rules! hal {
211211

212212
// Define the direction of the channel (input/output)
213213
// and the used input
214-
// 01: CC1 channel is configured as input, IC1 is mapped on TI1.
215-
// 10: CC1 channel is configured as input, IC1 is mapped on TI2.
216-
tim.ccmr1_output.modify( |_,w| unsafe {w.cc1s().bits(0b01)});
217-
218-
// 01: CC2 channel is configured as input, IC2 is mapped on TI2
219-
// 10: CC2 channel is configured as input, IC2 is mapped on TI1
220-
tim.ccmr1_output.modify( |_,w| unsafe {w.cc2s().bits(0b10)});
214+
tim.ccmr1_input().modify( |_,w| w.cc1s().ti1().cc2s().ti1());
221215

222216
tim.dier.write(|w| w.cc1ie().set_bit());
223217

@@ -236,25 +230,25 @@ macro_rules! hal {
236230
let max_freq = if freq > 5 {freq/5} else {1};
237231
let (arr,presc) = compute_arr_presc(max_freq, $TIMX::get_clk(&clocks).0);
238232
tim.arr.write(|w| w.arr().bits(arr));
239-
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
233+
tim.psc.write(|w| w.psc().bits(presc) );
240234

241235
},
242236
DutyCycle(f) => {
243237
let freq = f.into().0;
244238
let max_freq = if freq > 2 {freq/2 + freq/4 + freq/8} else {1};
245239
let (arr,presc) = compute_arr_presc(max_freq, $TIMX::get_clk(&clocks).0);
246240
tim.arr.write(|w| w.arr().bits(arr));
247-
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
241+
tim.psc.write(|w| w.psc().bits(presc) );
248242
},
249243
RawFrequency(f) => {
250244
let freq = f.into().0;
251245
let (arr,presc) = compute_arr_presc(freq, $TIMX::get_clk(&clocks).0);
252246
tim.arr.write(|w| w.arr().bits(arr));
253-
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
247+
tim.psc.write(|w| w.psc().bits(presc) );
254248
}
255249
RawValues{arr, presc} => {
256250
tim.arr.write(|w| w.arr().bits(arr));
257-
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
251+
tim.psc.write(|w| w.psc().bits(presc) );
258252

259253
}
260254
}

‎src/qei.rs‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,8 +78,7 @@ macro_rules! hal {
7878
apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
7979

8080
// Configure TxC1 and TxC2 as captures
81-
tim.ccmr1_output
82-
.write(|w| unsafe { w.bits({ (0b01 << 0) | (0b01 << 8) }) });
81+
tim.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2());
8382

8483
// enable and configure to capture on rising edge
8584
tim.ccer.write(|w| {

‎src/rcc.rs‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -194,12 +194,12 @@ impl CFGR {
194194
0 => unreachable!(),
195195
1 => 0b0111,
196196
2 => 0b1000,
197-
3...5 => 0b1001,
198-
6...11 => 0b1010,
199-
12...39 => 0b1011,
200-
40...95 => 0b1100,
201-
96...191 => 0b1101,
202-
192...383 => 0b1110,
197+
3..=5 => 0b1001,
198+
6..=11 => 0b1010,
199+
12..=39 => 0b1011,
200+
40..=95 => 0b1100,
201+
96..=191 => 0b1101,
202+
192..=383 => 0b1110,
203203
_ => 0b1111,
204204
})
205205
.unwrap_or(0b0111);
@@ -218,8 +218,8 @@ impl CFGR {
218218
0 => unreachable!(),
219219
1 => 0b011,
220220
2 => 0b100,
221-
3...5 => 0b101,
222-
6...11 => 0b110,
221+
3..=5 => 0b101,
222+
6..=11 => 0b110,
223223
_ => 0b111,
224224
})
225225
.unwrap_or(0b011);
@@ -235,8 +235,8 @@ impl CFGR {
235235
0 => unreachable!(),
236236
1 => 0b011,
237237
2 => 0b100,
238-
3...5 => 0b101,
239-
6...11 => 0b110,
238+
3..=5 => 0b101,
239+
6..=11 => 0b110,
240240
_ => 0b111,
241241
})
242242
.unwrap_or(0b011);
@@ -272,9 +272,9 @@ impl CFGR {
272272
let apre_bits = self
273273
.adcclk
274274
.map(|adcclk| match pclk2 / adcclk {
275-
0...2 => 0b00,
276-
3...4 => 0b01,
277-
5...7 => 0b10,
275+
0..=2 => 0b00,
276+
3..=4 => 0b01,
277+
5..=7 => 0b10,
278278
_ => 0b11,
279279
})
280280
.unwrap_or(0b11);
@@ -297,12 +297,12 @@ impl CFGR {
297297
if let Some(pllmul_bits) = pllmul_bits {
298298
// enable PLL and wait for it to be ready
299299

300-
rcc.cfgr.modify(|_, w| unsafe {
300+
rcc.cfgr.modify(|_, w|
301301
w.pllmul()
302302
.bits(pllmul_bits)
303303
.pllsrc()
304304
.bit(if self.hse.is_some() { true } else { false })
305-
});
305+
);
306306

307307
rcc.cr.modify(|_, w| w.pllon().set_bit());
308308

‎src/serial.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -566,8 +566,8 @@ macro_rules! serialdma {
566566
self.channel.ch().cr.modify(|_, w| { w
567567
.mem2mem() .clear_bit()
568568
.pl() .medium()
569-
.msize() .bit8()
570-
.psize() .bit8()
569+
.msize() .bits8()
570+
.psize() .bits8()
571571
.circ() .set_bit()
572572
.dir() .clear_bit()
573573
});
@@ -593,8 +593,8 @@ macro_rules! serialdma {
593593
self.channel.ch().cr.modify(|_, w| { w
594594
.mem2mem() .clear_bit()
595595
.pl() .medium()
596-
.msize() .bit8()
597-
.psize() .bit8()
596+
.msize() .bits8()
597+
.psize() .bits8()
598598
.circ() .clear_bit()
599599
.dir() .clear_bit()
600600
});
@@ -622,8 +622,8 @@ macro_rules! serialdma {
622622
self.channel.ch().cr.modify(|_, w| { w
623623
.mem2mem() .clear_bit()
624624
.pl() .medium()
625-
.msize() .bit8()
626-
.psize() .bit8()
625+
.msize() .bits8()
626+
.psize() .bits8()
627627
.circ() .clear_bit()
628628
.dir() .set_bit()
629629
});
@@ -655,4 +655,4 @@ serialdma! {
655655
dma1::C3,
656656
dma1::C2,
657657
),
658-
}
658+
}

‎src/spi.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -123,13 +123,13 @@ macro_rules! hal {
123123

124124
let br = match clocks.pclk2().0 / freq.0 {
125125
0 => unreachable!(),
126-
1...2 => 0b000,
127-
3...5 => 0b001,
128-
6...11 => 0b010,
129-
12...23 => 0b011,
130-
24...47 => 0b100,
131-
48...95 => 0b101,
132-
96...191 => 0b110,
126+
1..=2 => 0b000,
127+
3..=5 => 0b001,
128+
6..=11 => 0b010,
129+
12..=23 => 0b011,
130+
24..=47 => 0b100,
131+
48..=95 => 0b101,
132+
96..=191 => 0b110,
133133
_ => 0b111,
134134
};
135135

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