Add support for UART4/5

Author: burrbull

CHANGELOG.md

@@ -38,6 +38,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- `Serial` support for UART4/5
 - Allow to set HSE bypass bit in `RCC` clock configuration register to use an external clock input on the `OSC_IN` pin [#485]
 - initial support of `embedded-hal-1.0` [#416]
 - Add tools/check.py python script for local check [#467]

Cargo.toml

@@ -36,7 +36,7 @@ vcell = "0.1.3"
 
 [dependencies.stm32f1]
 package = "stm32f1-staging"
-version = "0.17.1"
+version = "0.19.0"
 features = ["atomics"]
 
 [dependencies.embedded-hal-02]

examples/can-echo.rs

@@ -29,11 +29,10 @@ fn main() -> ! {
         let rx = gpioa.pa11;
         let tx = gpioa.pa12;
 
-        let can = dp.CAN1.can(
-            #[cfg(not(feature = "connectivity"))]
-            dp.USB,
-            (tx, rx),
-        );
+        #[cfg(not(feature = "connectivity"))]
+        let can = dp.CAN.can(dp.USB, (tx, rx));
+        #[cfg(feature = "connectivity")]
+        let can = dp.CAN1.can((tx, rx));
 
         // APB1 (PCLK1): 8MHz, Bit rate: 125kBit/s, Sample Point 87.5%
         // Value was calculated with http://www.bittiming.can-wiki.info/

examples/can-loopback.rs

@@ -25,11 +25,10 @@ fn main() -> ! {
     // resonator must be used.
     rcc.cfgr.use_hse(8.MHz()).freeze(&mut flash.acr);
 
-    let can = Can::<_, Floating>::new_loopback(
-        dp.CAN1,
-        #[cfg(not(feature = "connectivity"))]
-        dp.USB,
-    );
+    #[cfg(not(feature = "connectivity"))]
+    let can = Can::<_, Floating>::new_loopback(dp.CAN, dp.USB);
+    #[cfg(feature = "connectivity")]
+    let can = Can::<_, Floating>::new_loopback(dp.CAN1);
 
     // Use loopback mode: No pins need to be assigned to peripheral.
     // APB1 (PCLK1): 8MHz, Bit rate: 500Bit/s, Sample Point 87.5%

examples/can-rtic.rs

@@ -55,7 +55,11 @@ mod app {
     use super::{enqueue_frame, PriorityFrame};
     use bxcan::{filter::Mask32, ExtendedId, Fifo, Frame, Interrupts, Rx0, StandardId, Tx};
     use heapless::binary_heap::{BinaryHeap, Max};
-    use stm32f1xx_hal::{can::Can, pac::CAN1, prelude::*};
+    #[cfg(not(feature = "connectivity"))]
+    use stm32f1xx_hal::pac::CAN as CAN1;
+    #[cfg(feature = "connectivity")]
+    use stm32f1xx_hal::pac::CAN1;
+    use stm32f1xx_hal::{can::Can, prelude::*};
 
     #[local]
     struct Local {
@@ -88,7 +92,7 @@ mod app {
         let can_tx_pin = gpioa.pa12;
 
         #[cfg(not(feature = "connectivity"))]
-        let can = Can::new(cx.device.CAN1, cx.device.USB, (can_tx_pin, can_rx_pin));
+        let can = Can::new(cx.device.CAN, cx.device.USB, (can_tx_pin, can_rx_pin));
 
         #[cfg(feature = "connectivity")]
         let can = Can::new(cx.device.CAN1, (can_tx_pin, can_rx_pin));

src/afio.rs

@@ -215,7 +215,7 @@ remap! {
 
 #[cfg(feature = "stm32f103")]
 remap! {
-    pac::CAN1: MAPR, u8: can_remap, { 0 | 2 | 3 };
+    pac::CAN: MAPR, u8: can_remap, { 0 | 2 | 3 };
 }
 
 #[cfg(feature = "connectivity")]
@@ -303,7 +303,11 @@ pub mod can1 {
         ],
     }
 
-    impl CanCommon for pac::CAN1 {
+    #[cfg(not(feature = "connectivity"))]
+    use pac::CAN as CAN1;
+    #[cfg(feature = "connectivity")]
+    use pac::CAN1;
+    impl CanCommon for CAN1 {
         type Tx = Tx;
         type Rx<PULL> = Rx<PULL>;
     }

src/can.rs

@@ -58,7 +58,12 @@ impl<CAN: Instance> CanExt for CAN {
 }
 
 pub trait Instance: crate::rcc::Enable + afio::CanCommon {}
-impl Instance for pac::CAN1 {}
+#[cfg(not(feature = "connectivity"))]
+use pac::CAN as CAN1;
+#[cfg(feature = "connectivity")]
+use pac::CAN1;
+
+impl Instance for CAN1 {}
 #[cfg(feature = "connectivity")]
 impl Instance for pac::CAN2 {}
 
@@ -125,18 +130,18 @@ impl<CAN: Instance, PULL: UpMode> Can<CAN, PULL> {
     }
 }
 
-unsafe impl<PULL> bxcan::Instance for Can<pac::CAN1, PULL> {
-    const REGISTERS: *mut bxcan::RegisterBlock = pac::CAN1::ptr() as *mut _;
+unsafe impl<PULL> bxcan::Instance for Can<CAN1, PULL> {
+    const REGISTERS: *mut bxcan::RegisterBlock = CAN1::ptr() as *mut _;
 }
 
 #[cfg(feature = "connectivity")]
 unsafe impl<PULL> bxcan::Instance for Can<pac::CAN2, PULL> {
     const REGISTERS: *mut bxcan::RegisterBlock = pac::CAN2::ptr() as *mut _;
 }
 
-unsafe impl<PULL> bxcan::FilterOwner for Can<pac::CAN1, PULL> {
+unsafe impl<PULL> bxcan::FilterOwner for Can<CAN1, PULL> {
     const NUM_FILTER_BANKS: u8 = 28;
 }
 
 #[cfg(feature = "connectivity")]
-unsafe impl<PULL> bxcan::MasterInstance for Can<pac::CAN1, PULL> {}
+unsafe impl<PULL> bxcan::MasterInstance for Can<CAN1, PULL> {}

src/gpio.rs

@@ -223,7 +223,7 @@ mod sealed {
     }
 }
 
-use crate::pac::gpioa::crl::{CNF0 as Cnf, MODE0 as Mode};
+use crate::pac::gpioa::crl::{CONFIG as Cnf, MODE as Mode};
 
 use sealed::Interruptable;
 pub(crate) use sealed::PinMode;

src/lib.rs

@@ -157,3 +157,18 @@ mod sealed {
     pub trait Sealed {}
 }
 use sealed::Sealed;
+use stm32f1::Periph;
+
+pub trait Ptr {
+    /// RegisterBlock structure
+    type RB;
+    /// Return the pointer to the register block
+    fn ptr() -> *const Self::RB;
+}
+
+impl<RB, const ADDR: usize> Ptr for Periph<RB, ADDR> {
+    type RB = RB;
+    fn ptr() -> *const Self::RB {
+        Self::ptr()
+    }
+}

src/rcc/enable.rs

@@ -65,7 +65,7 @@ macro_rules! ahb_bus {
 #[cfg(feature = "stm32f103")]
 bus! {
     ADC2 => (APB2, 10),
-    CAN1 => (APB1, 25),
+    CAN => (APB1, 25),
 }
 #[cfg(feature = "connectivity")]
 bus! {