Merge pull request #435 from stm32-rs/gpio_h

updates

Author: burrbull

.vscode/settings.json

@@ -0,0 +1,20 @@
+{
+  "rust.all_targets": false,
+  "rust.target": "thumbv7em-none-eabi",
+  "rust.all_features": false,
+  "rust.features": [
+    "rtic",
+    "stm32f103",
+    "medium"
+  ],
+  "rust-analyzer.checkOnSave.allTargets": false,
+  "rust-analyzer.checkOnSave.extraArgs": [
+      "--target",
+      "thumbv7em-none-eabi"
+  ],
+  "rust-analyzer.cargo.features": [
+    "rtic",
+    "stm32f103",
+    "medium"
+  ]
+}

examples/gpio_input.rs

@@ -60,8 +60,8 @@ fn main() -> ! {
             key_up = false;
             delay.delay_ms(10u8);
             match key_result {
-                (x, _) if x == true => red_led.toggle(),
-                (_, y) if y == true => green_led.toggle(),
+                (true, _) => red_led.toggle(),
+                (_, true) => green_led.toggle(),
                 (_, _) => (),
             }
         } else if !key_result.0 && !key_result.1 {

src/adc.rs

@@ -28,11 +28,11 @@ pub struct Adc<ADC> {
     clocks: Clocks,
 }
 
-#[derive(Clone, Copy, Debug, PartialEq)]
-#[allow(non_camel_case_types)]
 /// ADC sampling time
 ///
 /// Options for the sampling time, each is T + 0.5 ADC clock cycles.
+#[allow(non_camel_case_types)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub enum SampleTime {
     /// 1.5 cycles sampling time
     T_1,
@@ -75,7 +75,7 @@ impl From<SampleTime> for u8 {
     }
 }
 
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 /// ADC data register alignment
 pub enum Align {
     /// Right alignment of output data
@@ -169,7 +169,7 @@ adc_pins!(pac::ADC3,
 );
 
 /// Stored ADC config can be restored using the `Adc::restore_cfg` method
-#[derive(Copy, Clone, Debug, PartialEq, Default)]
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Default)]
 pub struct StoredConfig(SampleTime, Align);
 
 macro_rules! adc_hal {

src/bb.rs

@@ -18,6 +18,7 @@ const PERI_BIT_BAND_BASE: usize = 0x4200_0000;
 /// # Safety
 ///
 /// Some registers have reserved bits which should not be modified.
+#[inline]
 pub unsafe fn clear<T>(register: *const T, bit: u8) {
     write(register, bit, false);
 }
@@ -27,6 +28,7 @@ pub unsafe fn clear<T>(register: *const T, bit: u8) {
 /// # Safety
 ///
 /// Some registers have reserved bits which should not be modified.
+#[inline]
 pub unsafe fn set<T>(register: *const T, bit: u8) {
     write(register, bit, true);
 }
@@ -36,6 +38,7 @@ pub unsafe fn set<T>(register: *const T, bit: u8) {
 /// # Safety
 ///
 /// Some registers have reserved bits which should not be modified.
+#[inline]
 pub unsafe fn write<T>(register: *const T, bit: u8, set: bool) {
     let addr = register as usize;
 

src/dma.rs

@@ -13,12 +13,13 @@ pub enum Error {
     Overrun,
 }
 
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub enum Event {
     HalfTransfer,
     TransferComplete,
 }
 
-#[derive(Clone, Copy, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub enum Half {
     First,
     Second,

src/gpio.rs

@@ -312,7 +312,7 @@ impl Default for Dynamic {
 
 impl Active for Dynamic {}
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinModeError {
     IncorrectMode,
 }

src/i2c.rs

@@ -40,7 +40,7 @@ pub enum DutyCycle {
     Ratio16to9,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum Mode {
     Standard {
         frequency: Hertz,

src/rcc.rs

@@ -107,7 +107,7 @@ const HSI: u32 = 8_000_000; // Hz
 ///
 /// **NOTE**: Currently, it is not guaranteed that the exact frequencies selected will be
 /// used, only frequencies close to it.
-#[derive(Debug, Default, PartialEq)]
+#[derive(Debug, Default, PartialEq, Eq)]
 pub struct CFGR {
     hse: Option<u32>,
     hclk: Option<u32>,
@@ -334,7 +334,7 @@ impl BKP {
 ///
 /// let clocks = rcc.cfgr.freeze(&mut flash.acr);
 /// ```
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub struct Clocks {
     hclk: Hertz,
     pclk1: Hertz,

src/time.rs

@@ -35,7 +35,7 @@ use cortex_m::peripheral::{DCB, DWT};
 use crate::rcc::Clocks;
 
 /// Bits per second
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Bps(pub u32);
 
 pub use fugit::{
@@ -134,7 +134,6 @@ impl MonoTimer {
         dwt.enable_cycle_counter();
 
         // now the CYCCNT counter can't be stopped or reset
-        drop(dwt);
 
         MonoTimer {
             frequency: clocks.hclk(),

src/timer.rs

@@ -81,7 +81,7 @@ pub struct Timer<TIM> {
     pub(crate) clk: Hertz,
 }
 
-#[derive(Clone, Copy, PartialEq)]
+#[derive(Clone, Copy, PartialEq, Eq)]
 #[repr(u8)]
 pub enum Channel {
     C1 = 0,
@@ -91,7 +91,7 @@ pub enum Channel {
 }
 
 /// Interrupt events
-#[derive(Clone, Copy, PartialEq)]
+#[derive(Clone, Copy, PartialEq, Eq)]
 pub enum SysEvent {
     /// [Timer] timed out / count down ended
     Update,
@@ -245,7 +245,7 @@ impl Timer<SYST> {
     }
 }
 
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum Ocm {
     Frozen = 0,