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burrbullburrbull
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fmt spi
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2 files changed

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‎CHANGELOG.md‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1515
- `PwmHz::get_period`: fix computation of return value, prevent division by zero
1616
- return `i2c::Error::Timeout` instead of `nb::WouldBlock` when time is out
1717
- support `embedded-hal-1.0-alpha`
18-
- `gpio`: port and pin generics first, then mode, `PinMode` for modes instead of pins, other cleanups
1918

2019
### Breaking changes
2120

‎src/spi.rs‎

Lines changed: 92 additions & 159 deletions
Original file line numberDiff line numberDiff line change
@@ -370,8 +370,6 @@ where
370370
loop {
371371
let sr = self.spi.sr.read();
372372
if sr.txe().bit_is_set() {
373-
// NOTE(write_volatile) see note above
374-
// unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u8, *word) }
375373
self.write_data_reg(*word);
376374
if sr.modf().bit_is_set() {
377375
return Err(Error::ModeFault);
@@ -381,24 +379,10 @@ where
381379
}
382380
}
383381
// Wait for final TXE
384-
loop {
385-
let sr = self.spi.sr.read();
386-
if sr.txe().bit_is_set() {
387-
break;
388-
}
389-
}
382+
while self.spi.sr.read().txe().bit_is_clear() {}
390383
// Wait for final !BSY
391-
loop {
392-
let sr = self.spi.sr.read();
393-
if !sr.bsy().bit_is_set() {
394-
break;
395-
}
396-
}
384+
while self.spi.sr.read().bsy().bit_is_set() {}
397385
// Clear OVR set due to dropped received values
398-
// NOTE(read_volatile) see note above
399-
// unsafe {
400-
// let _ = ptr::read_volatile(&self.spi.dr as *const _ as *const u8);
401-
// }
402386
let _ = self.read_data_reg();
403387
let _ = self.spi.sr.read();
404388
Ok(())
@@ -490,40 +474,28 @@ where
490474
};
491475

492476
spi.cr1.write(|w| {
493-
w
494-
// clock phase from config
495-
.cpha()
496-
.bit(mode.phase == Phase::CaptureOnSecondTransition)
497-
// clock polarity from config
498-
.cpol()
499-
.bit(mode.polarity == Polarity::IdleHigh)
500-
// mstr: master configuration
501-
.mstr()
502-
.set_bit()
503-
// baudrate value
504-
.br()
505-
.bits(br)
506-
// lsbfirst: MSB first
507-
.lsbfirst()
508-
.clear_bit()
509-
// ssm: enable software slave management (NSS pin free for other uses)
510-
.ssm()
511-
.set_bit()
512-
// ssi: set nss high = master mode
513-
.ssi()
514-
.set_bit()
515-
// dff: 8 bit frames
516-
.dff()
517-
.clear_bit()
518-
// bidimode: 2-line unidirectional
519-
.bidimode()
520-
.clear_bit()
521-
// both TX and RX are used
522-
.rxonly()
523-
.clear_bit()
524-
// spe: enable the SPI bus
525-
.spe()
526-
.set_bit()
477+
// clock phase from config
478+
w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition);
479+
// clock polarity from config
480+
w.cpol().bit(mode.polarity == Polarity::IdleHigh);
481+
// mstr: master configuration
482+
w.mstr().set_bit();
483+
// baudrate value
484+
w.br().bits(br);
485+
// lsbfirst: MSB first
486+
w.lsbfirst().clear_bit();
487+
// ssm: enable software slave management (NSS pin free for other uses)
488+
w.ssm().set_bit();
489+
// ssi: set nss high = master mode
490+
w.ssi().set_bit();
491+
// dff: 8 bit frames
492+
w.dff().clear_bit();
493+
// bidimode: 2-line unidirectional
494+
w.bidimode().clear_bit();
495+
// both TX and RX are used
496+
w.rxonly().clear_bit();
497+
// spe: enable the SPI bus
498+
w.spe().set_bit()
527499
});
528500

529501
Spi {
@@ -550,37 +522,26 @@ where
550522
spi.cr2.write(|w| w.ssoe().clear_bit());
551523

552524
spi.cr1.write(|w| {
553-
w
554-
// clock phase from config
555-
.cpha()
556-
.bit(mode.phase == Phase::CaptureOnSecondTransition)
557-
// clock polarity from config
558-
.cpol()
559-
.bit(mode.polarity == Polarity::IdleHigh)
560-
// mstr: slave configuration
561-
.mstr()
562-
.clear_bit()
563-
// lsbfirst: MSB first
564-
.lsbfirst()
565-
.clear_bit()
566-
// ssm: enable software slave management (NSS pin free for other uses)
567-
.ssm()
568-
.set_bit()
569-
// ssi: set nss low = slave mode
570-
.ssi()
571-
.clear_bit()
572-
// dff: 8 bit frames
573-
.dff()
574-
.clear_bit()
575-
// bidimode: 2-line unidirectional
576-
.bidimode()
577-
.clear_bit()
578-
// both TX and RX are used
579-
.rxonly()
580-
.clear_bit()
581-
// spe: enable the SPI bus
582-
.spe()
583-
.set_bit()
525+
// clock phase from config
526+
w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition);
527+
// clock polarity from config
528+
w.cpol().bit(mode.polarity == Polarity::IdleHigh);
529+
// mstr: slave configuration
530+
w.mstr().clear_bit();
531+
// lsbfirst: MSB first
532+
w.lsbfirst().clear_bit();
533+
// ssm: enable software slave management (NSS pin free for other uses)
534+
w.ssm().set_bit();
535+
// ssi: set nss low = slave mode
536+
w.ssi().clear_bit();
537+
// dff: 8 bit frames
538+
w.dff().clear_bit();
539+
// bidimode: 2-line unidirectional
540+
w.bidimode().clear_bit();
541+
// both TX and RX are used
542+
w.rxonly().clear_bit();
543+
// spe: enable the SPI bus
544+
w.spe().set_bit()
584545
});
585546

586547
Spi {
@@ -772,25 +733,18 @@ macro_rules! spi_dma {
772733

773734
atomic::compiler_fence(Ordering::Release);
774735
self.channel.ch().cr.modify(|_, w| {
775-
w
776-
// memory to memory mode disabled
777-
.mem2mem()
778-
.clear_bit()
779-
// medium channel priority level
780-
.pl()
781-
.medium()
782-
// 8-bit memory size
783-
.msize()
784-
.bits8()
785-
// 8-bit peripheral size
786-
.psize()
787-
.bits8()
788-
// circular mode disabled
789-
.circ()
790-
.clear_bit()
791-
// write to memory
792-
.dir()
793-
.clear_bit()
736+
// memory to memory mode disabled
737+
w.mem2mem().clear_bit();
738+
// medium channel priority level
739+
w.pl().medium();
740+
// 8-bit memory size
741+
w.msize().bits8();
742+
// 8-bit peripheral size
743+
w.psize().bits8();
744+
// circular mode disabled
745+
w.circ().clear_bit();
746+
// write to memory
747+
w.dir().clear_bit()
794748
});
795749
self.start();
796750

@@ -816,25 +770,18 @@ macro_rules! spi_dma {
816770

817771
atomic::compiler_fence(Ordering::Release);
818772
self.channel.ch().cr.modify(|_, w| {
819-
w
820-
// memory to memory mode disabled
821-
.mem2mem()
822-
.clear_bit()
823-
// medium channel priority level
824-
.pl()
825-
.medium()
826-
// 8-bit memory size
827-
.msize()
828-
.bits8()
829-
// 8-bit peripheral size
830-
.psize()
831-
.bits8()
832-
// circular mode disabled
833-
.circ()
834-
.clear_bit()
835-
// read from memory
836-
.dir()
837-
.set_bit()
773+
// memory to memory mode disabled
774+
w.mem2mem().clear_bit();
775+
// medium channel priority level
776+
w.pl().medium();
777+
// 8-bit memory size
778+
w.msize().bits8();
779+
// 8-bit peripheral size
780+
w.psize().bits8();
781+
// circular mode disabled
782+
w.circ().clear_bit();
783+
// read from memory
784+
w.dir().set_bit()
838785
});
839786
self.start();
840787

@@ -878,46 +825,32 @@ macro_rules! spi_dma {
878825

879826
atomic::compiler_fence(Ordering::Release);
880827
self.rxchannel.ch().cr.modify(|_, w| {
881-
w
882-
// memory to memory mode disabled
883-
.mem2mem()
884-
.clear_bit()
885-
// medium channel priority level
886-
.pl()
887-
.medium()
888-
// 8-bit memory size
889-
.msize()
890-
.bits8()
891-
// 8-bit peripheral size
892-
.psize()
893-
.bits8()
894-
// circular mode disabled
895-
.circ()
896-
.clear_bit()
897-
// write to memory
898-
.dir()
899-
.clear_bit()
828+
// memory to memory mode disabled
829+
w.mem2mem().clear_bit();
830+
// medium channel priority level
831+
w.pl().medium();
832+
// 8-bit memory size
833+
w.msize().bits8();
834+
// 8-bit peripheral size
835+
w.psize().bits8();
836+
// circular mode disabled
837+
w.circ().clear_bit();
838+
// write to memory
839+
w.dir().clear_bit()
900840
});
901841
self.txchannel.ch().cr.modify(|_, w| {
902-
w
903-
// memory to memory mode disabled
904-
.mem2mem()
905-
.clear_bit()
906-
// medium channel priority level
907-
.pl()
908-
.medium()
909-
// 8-bit memory size
910-
.msize()
911-
.bits8()
912-
// 8-bit peripheral size
913-
.psize()
914-
.bits8()
915-
// circular mode disabled
916-
.circ()
917-
.clear_bit()
918-
// read from memory
919-
.dir()
920-
.set_bit()
842+
// memory to memory mode disabled
843+
w.mem2mem().clear_bit();
844+
// medium channel priority level
845+
w.pl().medium();
846+
// 8-bit memory size
847+
w.msize().bits8();
848+
// 8-bit peripheral size
849+
w.psize().bits8();
850+
// circular mode disabled
851+
w.circ().clear_bit();
852+
// read from memory
853+
w.dir().set_bit()
921854
});
922855
self.start();
923856

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