From e3e62f3ba78ec209d8d14e3217686225555bf0fa Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Sat, 5 Oct 2024 14:04:37 +0300 Subject: [PATCH] stm32f1-staging --- CHANGELOG.md | 1 + Cargo.toml | 8 +- examples/blinky_rtcalarm_irq.rs | 6 +- src/adc.rs | 148 ++++++++++++++++-------------- src/afio.rs | 14 +-- src/backup_domain.rs | 4 +- src/crc.rs | 6 +- src/dac.rs | 6 +- src/dma.rs | 32 +++---- src/flash.rs | 16 ++-- src/gpio.rs | 36 ++++---- src/gpio/partially_erased.rs | 10 +-- src/i2c.rs | 30 +++---- src/i2c/blocking.rs | 66 +++++++------- src/qei.rs | 12 +-- src/rcc.rs | 38 ++++---- src/rtc.rs | 120 ++++++++++++------------- src/serial.rs | 84 ++++++++++-------- src/spi.rs | 153 +++++++++++++++++--------------- src/timer.rs | 92 +++++++++---------- src/timer/monotonic.rs | 24 ++--- src/timer/pwm_input.rs | 32 +++---- src/watchdog.rs | 20 ++--- 23 files changed, 493 insertions(+), 465 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 2c755adb..f9c7a086 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). Remove `RemapStruct`s. [#462] - Use independent `Spi` and `SpiSlave` structures instead of `OP` generic [#462] - Take `&Clocks` instead of `Clocks` [#498] +- Temporary replace `stm32f1` with `stm32f1-staging` ### Changed diff --git a/Cargo.toml b/Cargo.toml index aee47715..fe5f5c9a 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -21,7 +21,6 @@ default-target = "x86_64-unknown-linux-gnu" cortex-m = "0.7.6" cortex-m-rt = "0.7.1" nb = "1.1" -stm32f1 = "0.15.1" embedded-dma = "0.2.0" bxcan = "0.7" void = { default-features = false, version = "1.0.2" } @@ -31,6 +30,11 @@ rtic-monotonic = { version = "1.0", optional = true } bitflags = "1.3.2" vcell = "0.1.3" +[dependencies.stm32f1] +package = "stm32f1-staging" +version = "0.16.0" +features = ["atomics"] + [dependencies.embedded-hal-02] package = "embedded-hal" version = "0.2.7" @@ -68,6 +72,8 @@ stm32f103 = ["stm32f1/stm32f103", "has-can", "stm32-usbd"] stm32f105 = ["stm32f1/stm32f107", "connectivity"] stm32f107 = ["stm32f1/stm32f107", "connectivity"] +defmt = ["stm32f1/defmt"] + # Devices with 64 or 128 Kb ROM medium = [] # Devices with 256 or 512 Kb ROM diff --git a/examples/blinky_rtcalarm_irq.rs b/examples/blinky_rtcalarm_irq.rs index 4aab935c..23be255a 100644 --- a/examples/blinky_rtcalarm_irq.rs +++ b/examples/blinky_rtcalarm_irq.rs @@ -66,7 +66,7 @@ fn RTCALARM() { cortex_m::interrupt::free(|cs| G_EXTI.borrow(cs).replace(None).unwrap()) }); - exti.pr.write(|w| w.pr17().set_bit()); + exti.pr().write(|w| w.pr17().clear_bit_by_one()); rtc.set_alarm(rtc.current_time() + TOGGLE_INTERVAL_SECONDS); let _ = led.toggle(); @@ -89,8 +89,8 @@ fn main() -> ! { // Set up the EXTI (see notes in section 18.4.2 of reference manual) let exti = dp.EXTI; - exti.ftsr.write(|w| w.tr17().set_bit()); - exti.imr.write(|w| w.mr17().set_bit()); + exti.ftsr().write(|w| w.tr17().set_bit()); + exti.imr().write(|w| w.mr17().set_bit()); cortex_m::interrupt::free(|cs| *G_EXTI.borrow(cs).borrow_mut() = Some(exti)); diff --git a/src/adc.rs b/src/adc.rs index 595019e3..e79c911b 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -255,12 +255,12 @@ macro_rules! adc_hal { } #[inline(always)] - pub fn set_external_trigger(&mut self, trigger: crate::pac::$adc::cr2::EXTSEL_A) { - self.rb.cr2.modify(|_, w| w.extsel().variant(trigger)) + pub fn set_external_trigger(&mut self, trigger: crate::pac::$adc::cr2::EXTSEL) { + self.rb.cr2().modify(|_, w| w.extsel().variant(trigger)) } fn power_up(&mut self) { - self.rb.cr2.modify(|_, w| w.adon().set_bit()); + self.rb.cr2().modify(|_, w| w.adon().set_bit()); // The reference manual says that a stabilization time is needed after power_up, // this time can be found in the datasheets. @@ -270,7 +270,7 @@ macro_rules! adc_hal { } fn power_down(&mut self) { - self.rb.cr2.modify(|_, w| w.adon().clear_bit()); + self.rb.cr2().modify(|_, w| w.adon().clear_bit()); } fn reset(&mut self) { @@ -290,51 +290,51 @@ macro_rules! adc_hal { fn calibrate(&mut self) { /* reset calibration */ - self.rb.cr2.modify(|_, w| w.rstcal().set_bit()); - while self.rb.cr2.read().rstcal().bit_is_set() {} + self.rb.cr2().modify(|_, w| w.rstcal().set_bit()); + while self.rb.cr2().read().rstcal().bit_is_set() {} /* calibrate */ - self.rb.cr2.modify(|_, w| w.cal().set_bit()); - while self.rb.cr2.read().cal().bit_is_set() {} + self.rb.cr2().modify(|_, w| w.cal().set_bit()); + while self.rb.cr2().read().cal().bit_is_set() {} } fn setup_oneshot(&mut self) { - self.rb.cr2.modify(|_, w| w + self.rb.cr2().modify(|_, w| w .cont().clear_bit() .exttrig().set_bit() - .extsel().bits(0b111) + .extsel().swstart() ); - self.rb.cr1.modify(|_, w| w + self.rb.cr1().modify(|_, w| w .scan().clear_bit() .discen().set_bit() ); - self.rb.sqr1.modify(|_, w| w.l().bits(0b0)); + self.rb.sqr1().modify(|_, w| w.l().set(0b0)); } fn set_channel_sample_time(&mut self, chan: u8, sample_time: SampleTime) { let sample_time = sample_time.into(); match chan { - 0 => self.rb.smpr2.modify(|_, w| w.smp0().bits(sample_time)), - 1 => self.rb.smpr2.modify(|_, w| w.smp1().bits(sample_time)), - 2 => self.rb.smpr2.modify(|_, w| w.smp2().bits(sample_time)), - 3 => self.rb.smpr2.modify(|_, w| w.smp3().bits(sample_time)), - 4 => self.rb.smpr2.modify(|_, w| w.smp4().bits(sample_time)), - 5 => self.rb.smpr2.modify(|_, w| w.smp5().bits(sample_time)), - 6 => self.rb.smpr2.modify(|_, w| w.smp6().bits(sample_time)), - 7 => self.rb.smpr2.modify(|_, w| w.smp7().bits(sample_time)), - 8 => self.rb.smpr2.modify(|_, w| w.smp8().bits(sample_time)), - 9 => self.rb.smpr2.modify(|_, w| w.smp9().bits(sample_time)), - - 10 => self.rb.smpr1.modify(|_, w| w.smp10().bits(sample_time)), - 11 => self.rb.smpr1.modify(|_, w| w.smp11().bits(sample_time)), - 12 => self.rb.smpr1.modify(|_, w| w.smp12().bits(sample_time)), - 13 => self.rb.smpr1.modify(|_, w| w.smp13().bits(sample_time)), - 14 => self.rb.smpr1.modify(|_, w| w.smp14().bits(sample_time)), - 15 => self.rb.smpr1.modify(|_, w| w.smp15().bits(sample_time)), - 16 => self.rb.smpr1.modify(|_, w| w.smp16().bits(sample_time)), - 17 => self.rb.smpr1.modify(|_, w| w.smp17().bits(sample_time)), + 0 => self.rb.smpr2().modify(|_, w| w.smp0().set(sample_time)), + 1 => self.rb.smpr2().modify(|_, w| w.smp1().set(sample_time)), + 2 => self.rb.smpr2().modify(|_, w| w.smp2().set(sample_time)), + 3 => self.rb.smpr2().modify(|_, w| w.smp3().set(sample_time)), + 4 => self.rb.smpr2().modify(|_, w| w.smp4().set(sample_time)), + 5 => self.rb.smpr2().modify(|_, w| w.smp5().set(sample_time)), + 6 => self.rb.smpr2().modify(|_, w| w.smp6().set(sample_time)), + 7 => self.rb.smpr2().modify(|_, w| w.smp7().set(sample_time)), + 8 => self.rb.smpr2().modify(|_, w| w.smp8().set(sample_time)), + 9 => self.rb.smpr2().modify(|_, w| w.smp9().set(sample_time)), + + 10 => self.rb.smpr1().modify(|_, w| w.smp10().set(sample_time)), + 11 => self.rb.smpr1().modify(|_, w| w.smp11().set(sample_time)), + 12 => self.rb.smpr1().modify(|_, w| w.smp12().set(sample_time)), + 13 => self.rb.smpr1().modify(|_, w| w.smp13().set(sample_time)), + 14 => self.rb.smpr1().modify(|_, w| w.smp14().set(sample_time)), + 15 => self.rb.smpr1().modify(|_, w| w.smp15().set(sample_time)), + 16 => self.rb.smpr1().modify(|_, w| w.smp16().set(sample_time)), + 17 => self.rb.smpr1().modify(|_, w| w.smp17().set(sample_time)), _ => unreachable!(), } } @@ -344,14 +344,14 @@ macro_rules! adc_hal { let bits = channels.iter().take(6).enumerate().fold(0u32, |s, (i, c)| s | ((*c as u32) << (i * 5)) ); - self.rb.sqr3.write(|w| unsafe { w + self.rb.sqr3().write(|w| unsafe { w .bits( bits ) }); if len > 6 { let bits = channels.iter().skip(6).take(6).enumerate().fold(0u32, |s, (i, c)| s | ((*c as u32) << (i * 5)) ); - self.rb.sqr2.write(|w| unsafe { w + self.rb.sqr2().write(|w| unsafe { w .bits( bits ) }); } @@ -359,20 +359,20 @@ macro_rules! adc_hal { let bits = channels.iter().skip(12).take(4).enumerate().fold(0u32, |s, (i, c)| s | ((*c as u32) << (i * 5)) ); - self.rb.sqr1.write(|w| unsafe { w + self.rb.sqr1().write(|w| unsafe { w .bits( bits ) }); } - self.rb.sqr1.modify(|_, w| w.l().bits((len-1) as u8)); + self.rb.sqr1().modify(|_, w| w.l().set((len-1) as u8)); } fn set_continuous_mode(&mut self, continuous: bool) { - self.rb.cr2.modify(|_, w| w.cont().bit(continuous)); + self.rb.cr2().modify(|_, w| w.cont().bit(continuous)); } fn set_discontinuous_mode(&mut self, channels_count: Option) { - self.rb.cr1.modify(|_, w| match channels_count { - Some(count) => w.discen().set_bit().discnum().bits(count), + self.rb.cr1().modify(|_, w| match channels_count { + Some(count) => w.discen().set_bit().discnum().set(count), None => w.discen().clear_bit(), }); } @@ -394,22 +394,22 @@ macro_rules! adc_hal { // Dummy read in case something accidentally triggered // a conversion by writing to CR2 without changing any // of the bits - self.rb.dr.read().data().bits(); + self.rb.dr().read().data().bits(); self.set_channel_sample_time(chan, self.sample_time); - self.rb.sqr3.modify(|_, w| unsafe { w.sq1().bits(chan) }); + self.rb.sqr3().modify(|_, w| unsafe { w.sq1().bits(chan) }); // ADC start conversion of regular sequence - self.rb.cr2.modify(|_, w| + self.rb.cr2().modify(|_, w| w .swstart().set_bit() .align().bit(self.align.into()) ); - while self.rb.cr2.read().swstart().bit_is_set() {} + while self.rb.cr2().read().swstart().bit_is_set() {} // ADC wait for conversion results - while self.rb.sr.read().eoc().bit_is_clear() {} + while self.rb.sr().read().eoc().bit_is_clear() {} - let res = self.rb.dr.read().data().bits(); + let res = self.rb.dr().read().data().bits(); res } @@ -459,8 +459,8 @@ macro_rules! adc_hal { impl Adc { fn read_aux(&mut self, chan: u8) -> u16 { - let tsv_off = if self.rb.cr2.read().tsvrefe().bit_is_clear() { - self.rb.cr2.modify(|_, w| w.tsvrefe().set_bit()); + let tsv_off = if self.rb.cr2().read().tsvrefe().bit_is_clear() { + self.rb.cr2().modify(|_, w| w.tsvrefe().set_bit()); // The reference manual says that a stabilization time is needed after the powering the // sensor, this time can be found in the datasheets. @@ -475,7 +475,7 @@ impl Adc { let val = self.convert(chan); if tsv_off { - self.rb.cr2.modify(|_, w| w.tsvrefe().clear_bit()); + self.rb.cr2().modify(|_, w| w.tsvrefe().clear_bit()); } val @@ -618,19 +618,23 @@ macro_rules! adcdma { impl TransferPayload for AdcDma<$ADCX, PINS, Continuous, $dmarxch> { fn start(&mut self) { self.channel.start(); - self.payload.adc.rb.cr2.modify(|_, w| w.cont().set_bit()); - self.payload.adc.rb.cr2.modify(|_, w| w.adon().set_bit()); + self.payload.adc.rb.cr2().modify(|_, w| w.cont().set_bit()); + self.payload.adc.rb.cr2().modify(|_, w| w.adon().set_bit()); } fn stop(&mut self) { self.channel.stop(); - self.payload.adc.rb.cr2.modify(|_, w| w.cont().clear_bit()); + self.payload + .adc + .rb + .cr2() + .modify(|_, w| w.cont().clear_bit()); } } impl TransferPayload for AdcDma<$ADCX, PINS, Scan, $dmarxch> { fn start(&mut self) { self.channel.start(); - self.payload.adc.rb.cr2.modify(|_, w| w.adon().set_bit()); + self.payload.adc.rb.cr2().modify(|_, w| w.adon().set_bit()); } fn stop(&mut self) { self.channel.stop(); @@ -646,13 +650,15 @@ macro_rules! adcdma { where PIN: Channel<$ADCX, ID = u8>, { - self.rb.cr1.modify(|_, w| w.discen().clear_bit()); - self.rb.cr2.modify(|_, w| w.align().bit(self.align.into())); + self.rb.cr1().modify(|_, w| w.discen().clear_bit()); + self.rb + .cr2() + .modify(|_, w| w.align().bit(self.align.into())); self.set_channel_sample_time(PIN::channel(), self.sample_time); self.rb - .sqr3 + .sqr3() .modify(|_, w| unsafe { w.sq1().bits(PIN::channel()) }); - self.rb.cr2.modify(|_, w| w.dma().set_bit()); + self.rb.cr2().modify(|_, w| w.dma().set_bit()); let payload = AdcPayload { adc: self, @@ -673,7 +679,7 @@ macro_rules! adcdma { where Self: SetChannels, { - self.rb.cr2.modify(|_, w| { + self.rb.cr2().modify(|_, w| { w.adon() .clear_bit() .dma() @@ -684,12 +690,12 @@ macro_rules! adcdma { .bit(self.align.into()) }); self.rb - .cr1 + .cr1() .modify(|_, w| w.scan().set_bit().discen().clear_bit()); self.set_samples(); self.set_sequence(); self.rb - .cr2 + .cr2() .modify(|_, w| w.dma().set_bit().adon().set_bit()); let payload = AdcPayload { @@ -712,8 +718,8 @@ macro_rules! adcdma { self.stop(); let AdcDma { payload, channel } = self; - payload.adc.rb.cr2.modify(|_, w| w.dma().clear_bit()); - payload.adc.rb.cr1.modify(|_, w| w.discen().set_bit()); + payload.adc.rb.cr2().modify(|_, w| w.dma().clear_bit()); + payload.adc.rb.cr1().modify(|_, w| w.discen().set_bit()); (payload.adc, payload.pins, channel) } @@ -727,9 +733,9 @@ macro_rules! adcdma { self.stop(); let AdcDma { payload, channel } = self; - payload.adc.rb.cr2.modify(|_, w| w.dma().clear_bit()); - payload.adc.rb.cr1.modify(|_, w| w.discen().set_bit()); - payload.adc.rb.cr1.modify(|_, w| w.scan().clear_bit()); + payload.adc.rb.cr2().modify(|_, w| w.dma().clear_bit()); + payload.adc.rb.cr1().modify(|_, w| w.discen().set_bit()); + payload.adc.rb.cr1().modify(|_, w| w.scan().clear_bit()); (payload.adc, payload.pins, channel) } @@ -745,14 +751,16 @@ macro_rules! adcdma { // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it // until the end of the transfer. let (ptr, len) = unsafe { buffer.write_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*<$ADCX>::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*<$ADCX>::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { w.mem2mem() .clear_bit() .pl() @@ -782,13 +790,15 @@ macro_rules! adcdma { // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it // until the end of the transfer. let (ptr, len) = unsafe { buffer.write_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*<$ADCX>::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*<$ADCX>::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { w.mem2mem() .clear_bit() .pl() diff --git a/src/afio.rs b/src/afio.rs index ef5c9359..2e1cfeda 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -57,7 +57,7 @@ pub struct EVCR { impl EVCR { pub fn evcr(&mut self) -> &afio::EVCR { - unsafe { &(*AFIO::ptr()).evcr } + unsafe { (*AFIO::ptr()).evcr() } } } @@ -78,7 +78,7 @@ pub struct MAPR { impl MAPR { fn mapr(&mut self) -> &afio::MAPR { - unsafe { &(*AFIO::ptr()).mapr } + unsafe { (*AFIO::ptr()).mapr() } } pub fn modify_mapr(&mut self, mod_fn: F) @@ -117,7 +117,7 @@ pub struct EXTICR1 { impl EXTICR1 { pub fn exticr1(&mut self) -> &afio::EXTICR1 { - unsafe { &(*AFIO::ptr()).exticr1 } + unsafe { (*AFIO::ptr()).exticr1() } } } @@ -127,7 +127,7 @@ pub struct EXTICR2 { impl EXTICR2 { pub fn exticr2(&mut self) -> &afio::EXTICR2 { - unsafe { &(*AFIO::ptr()).exticr2 } + unsafe { (*AFIO::ptr()).exticr2() } } } @@ -137,7 +137,7 @@ pub struct EXTICR3 { impl EXTICR3 { pub fn exticr3(&mut self) -> &afio::EXTICR3 { - unsafe { &(*AFIO::ptr()).exticr3 } + unsafe { (*AFIO::ptr()).exticr3() } } } @@ -147,7 +147,7 @@ pub struct EXTICR4 { impl EXTICR4 { pub fn exticr4(&mut self) -> &afio::EXTICR4 { - unsafe { &(*AFIO::ptr()).exticr4 } + unsafe { (*AFIO::ptr()).exticr4() } } } @@ -157,6 +157,6 @@ pub struct MAPR2 { impl MAPR2 { pub fn mapr2(&mut self) -> &afio::MAPR2 { - unsafe { &(*AFIO::ptr()).mapr2 } + unsafe { (*AFIO::ptr()).mapr2() } } } diff --git a/src/backup_domain.rs b/src/backup_domain.rs index b19b5f4e..d135cf43 100644 --- a/src/backup_domain.rs +++ b/src/backup_domain.rs @@ -25,13 +25,13 @@ pub struct BackupDomain { macro_rules! write_drx { ($self:ident, $drx:ident, $idx:expr, $new:expr) => { - $self._regs.$drx[$idx].write(|w| w.d().bits($new)) + $self._regs.$drx($idx).write(|w| w.d().set($new)) }; } macro_rules! read_drx { ($self:ident, $drx:ident, $idx:expr) => { - $self._regs.$drx[$idx].read().d().bits() + $self._regs.$drx($idx).read().d().bits() }; } diff --git a/src/crc.rs b/src/crc.rs index 252ee171..72d9ced5 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -26,15 +26,15 @@ pub struct Crc { impl Crc { pub fn read(&self) -> u32 { - self.crc.dr.read().bits() + self.crc.dr().read().bits() } pub fn write(&mut self, val: u32) { - self.crc.dr.write(|w| w.dr().bits(val)) + self.crc.dr().write(|w| w.dr().set(val)) } pub fn reset(&self) { - self.crc.cr.write(|w| w.reset().set_bit()); + self.crc.cr().write(|w| w.reset().set_bit()); // calling CRC::dr::write() just after CRC::cr::reset() will not work as expected, and // inserting single nop() seems to solve the problem. cortex_m::asm::nop(); diff --git a/src/dac.rs b/src/dac.rs index ea40063f..95c7d654 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -66,19 +66,19 @@ macro_rules! dac { impl DacPin for $CX { fn enable(&mut self) { let dac = unsafe { &(*DAC::ptr()) }; - dac.cr.modify(|_, w| w.$en().set_bit()); + dac.cr().modify(|_, w| w.$en().set_bit()); } } impl DacOut for $CX { fn set_value(&mut self, val: u16) { let dac = unsafe { &(*DAC::ptr()) }; - dac.$dhrx.write(|w| unsafe { w.bits(val as u32) }); + dac.$dhrx().write(|w| unsafe { w.bits(val as u32) }); } fn get_value(&mut self) -> u16 { let dac = unsafe { &(*DAC::ptr()) }; - dac.$dac_dor.read().bits() as u16 + dac.$dac_dor().read().bits() as u16 } } }; diff --git a/src/dma.rs b/src/dma.rs index b94ad9d3..a1184a93 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -144,32 +144,32 @@ macro_rules! dma { /// /// `inc` indicates whether the address will be incremented after every byte transfer pub fn set_peripheral_address(&mut self, address: u32, inc: bool) { - self.ch().par.write(|w| unsafe { w.pa().bits(address) } ); - self.ch().cr.modify(|_, w| w.pinc().bit(inc) ); + self.ch().par().write(|w| unsafe { w.pa().bits(address) } ); + self.ch().cr().modify(|_, w| w.pinc().bit(inc) ); } /// `address` where from/to data will be read/write /// /// `inc` indicates whether the address will be incremented after every byte transfer pub fn set_memory_address(&mut self, address: u32, inc: bool) { - self.ch().mar.write(|w| unsafe { w.ma().bits(address) } ); - self.ch().cr.modify(|_, w| w.minc().bit(inc) ); + self.ch().mar().write(|w| unsafe { w.ma().bits(address) } ); + self.ch().cr().modify(|_, w| w.minc().bit(inc) ); } /// Number of bytes to transfer pub fn set_transfer_length(&mut self, len: usize) { - self.ch().ndtr.write(|w| w.ndt().bits(u16::try_from(len).unwrap())); + self.ch().ndtr().write(|w| w.ndt().set(u16::try_from(len).unwrap())); } /// Starts the DMA transfer pub fn start(&mut self) { - self.ch().cr.modify(|_, w| w.en().set_bit() ); + self.ch().cr().modify(|_, w| w.en().set_bit() ); } /// Stops the DMA transfer pub fn stop(&mut self) { self.ifcr().write(|w| w.$cgifX().set_bit()); - self.ch().cr.modify(|_, w| w.en().clear_bit() ); + self.ch().cr().modify(|_, w| w.en().clear_bit() ); } /// Returns `true` if there's a transfer in progress @@ -181,9 +181,9 @@ macro_rules! dma { impl $CX { pub fn listen(&mut self, event: Event) { match event { - Event::HalfTransfer => self.ch().cr.modify(|_, w| w.htie().set_bit()), + Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().set_bit()), Event::TransferComplete => { - self.ch().cr.modify(|_, w| w.tcie().set_bit()) + self.ch().cr().modify(|_, w| w.tcie().set_bit()) } } } @@ -191,30 +191,30 @@ macro_rules! dma { pub fn unlisten(&mut self, event: Event) { match event { Event::HalfTransfer => { - self.ch().cr.modify(|_, w| w.htie().clear_bit()) + self.ch().cr().modify(|_, w| w.htie().clear_bit()) }, Event::TransferComplete => { - self.ch().cr.modify(|_, w| w.tcie().clear_bit()) + self.ch().cr().modify(|_, w| w.tcie().clear_bit()) } } } pub fn ch(&mut self) -> &dma1::CH { - unsafe { &(*$DMAX::ptr()).$chX } + unsafe { (*$DMAX::ptr()).$chX() } } pub fn isr(&self) -> dma1::isr::R { // NOTE(unsafe) atomic read with no side effects - unsafe { (*$DMAX::ptr()).isr.read() } + unsafe { (*$DMAX::ptr()).isr().read() } } pub fn ifcr(&self) -> &dma1::IFCR { - unsafe { &(*$DMAX::ptr()).ifcr } + unsafe { &(*$DMAX::ptr()).ifcr() } } pub fn get_ndtr(&self) -> u32 { // NOTE(unsafe) atomic read with no side effects - unsafe { &(*$DMAX::ptr())}.$chX.ndtr.read().bits() + unsafe { &(*$DMAX::ptr())}.$chX().ndtr().read().bits() } } @@ -453,7 +453,7 @@ macro_rules! dma { // reset the DMA control registers (stops all on-going transfers) $( - self.$chX.cr.reset(); + self.$chX().cr().reset(); )+ Channels((), $($CX { _0: () }),+) diff --git a/src/flash.rs b/src/flash.rs index 4dba3bed..cbf958e6 100644 --- a/src/flash.rs +++ b/src/flash.rs @@ -367,7 +367,7 @@ pub struct ACR { impl ACR { pub(crate) fn acr(&mut self) -> &flash::ACR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).acr } + unsafe { (*FLASH::ptr()).acr() } } } @@ -380,7 +380,7 @@ pub struct AR { impl AR { pub(crate) fn ar(&mut self) -> &flash::AR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).ar } + unsafe { (*FLASH::ptr()).ar() } } } @@ -393,7 +393,7 @@ pub struct CR { impl CR { pub(crate) fn cr(&mut self) -> &flash::CR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).cr } + unsafe { (*FLASH::ptr()).cr() } } } @@ -406,7 +406,7 @@ pub struct KEYR { impl KEYR { pub(crate) fn keyr(&mut self) -> &flash::KEYR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).keyr } + unsafe { (*FLASH::ptr()).keyr() } } } @@ -419,7 +419,7 @@ pub struct OBR { impl OBR { pub(crate) fn obr(&mut self) -> &flash::OBR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).obr } + unsafe { (*FLASH::ptr()).obr() } } } @@ -432,7 +432,7 @@ pub struct OPTKEYR { impl OPTKEYR { pub(crate) fn optkeyr(&mut self) -> &flash::OPTKEYR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).optkeyr } + unsafe { (*FLASH::ptr()).optkeyr() } } } @@ -445,7 +445,7 @@ pub struct SR { impl SR { pub(crate) fn sr(&mut self) -> &flash::SR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).sr } + unsafe { (*FLASH::ptr()).sr() } } } @@ -458,6 +458,6 @@ pub struct WRPR { impl WRPR { pub(crate) fn wrpr(&mut self) -> &flash::WRPR { // NOTE(unsafe) this proxy grants exclusive access to this register - unsafe { &(*FLASH::ptr()).wrpr } + unsafe { (*FLASH::ptr()).wrpr() } } } diff --git a/src/gpio.rs b/src/gpio.rs index 0d5ecebd..9abb5b8e 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -264,21 +264,21 @@ where let pin_number = self.pin_id(); match edge { Edge::Rising => { - exti.rtsr + exti.rtsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << pin_number)) }); - exti.ftsr + exti.ftsr() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << pin_number)) }); } Edge::Falling => { - exti.ftsr + exti.ftsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << pin_number)) }); - exti.rtsr + exti.rtsr() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << pin_number)) }); } Edge::RisingFalling => { - exti.rtsr + exti.rtsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << pin_number)) }); - exti.ftsr + exti.ftsr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << pin_number)) }); } } @@ -286,24 +286,24 @@ where /// Enable external interrupts from this pin. fn enable_interrupt(&mut self, exti: &mut EXTI) { - exti.imr + exti.imr() .modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.pin_id())) }); } /// Disable external interrupts from this pin fn disable_interrupt(&mut self, exti: &mut EXTI) { - exti.imr + exti.imr() .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id())) }); } /// Clear the interrupt pending bit for this pin fn clear_interrupt_pending_bit(&mut self) { - unsafe { (*EXTI::ptr()).pr.write(|w| w.bits(1 << self.pin_id())) }; + unsafe { (*EXTI::ptr()).pr().write(|w| w.bits(1 << self.pin_id())) }; } /// Reads the interrupt pending bit for this pin fn check_interrupt(&self) -> bool { - unsafe { ((*EXTI::ptr()).pr.read().bits() & (1 << self.pin_id())) != 0 } + unsafe { ((*EXTI::ptr()).pr().read().bits() & (1 << self.pin_id())) != 0 } } } @@ -518,25 +518,25 @@ impl Pin { #[inline(always)] fn _set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*Gpio::

::ptr()).bsrr.write(|w| w.bits(1 << N)) } + unsafe { (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << N)) } } #[inline(always)] fn _set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register - unsafe { (*Gpio::

::ptr()).bsrr.write(|w| w.bits(1 << (16 + N))) } + unsafe { (*Gpio::

::ptr()).bsrr().write(|w| w.bits(1 << (16 + N))) } } #[inline(always)] fn _is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).odr.read().bits() & (1 << N) == 0 } + unsafe { (*Gpio::

::ptr()).odr().read().bits() & (1 << N) == 0 } } #[inline(always)] fn _is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr.read().bits() & (1 << N) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << N) == 0 } } } @@ -821,10 +821,10 @@ where match N { 0..=7 => { - gpio.crl.modify(|r, w| unsafe { w.bits(f(r.bits())) }); + gpio.crl().modify(|r, w| unsafe { w.bits(f(r.bits())) }); } 8..=15 => { - gpio.crh.modify(|r, w| unsafe { w.bits(f(r.bits())) }); + gpio.crh().modify(|r, w| unsafe { w.bits(f(r.bits())) }); } _ => unreachable!(), } @@ -950,9 +950,9 @@ where // Input or Input mode if let Some(pull) = MODE::PULL { if pull { - gpio.bsrr.write(|w| unsafe { w.bits(1 << N) }); + gpio.bsrr().write(|w| unsafe { w.bits(1 << N) }); } else { - gpio.bsrr.write(|w| unsafe { w.bits(1 << (16 + N)) }); + gpio.bsrr().write(|w| unsafe { w.bits(1 << (16 + N)) }); } } diff --git a/src/gpio/partially_erased.rs b/src/gpio/partially_erased.rs index 094413db..b3153e0e 100644 --- a/src/gpio/partially_erased.rs +++ b/src/gpio/partially_erased.rs @@ -40,7 +40,7 @@ impl PartiallyErasedPin> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*Gpio::

::ptr()) - .bsrr + .bsrr() .write(|w| w.bits(1 << self.pin_number)) } } @@ -50,7 +50,7 @@ impl PartiallyErasedPin> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*Gpio::

::ptr()) - .bsrr + .bsrr() .write(|w| w.bits(1 << (self.pin_number + 16))) } } @@ -80,7 +80,7 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn is_set_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).odr.read().bits() & (1 << self.pin_number) == 0 } + unsafe { (*Gpio::

::ptr()).odr().read().bits() & (1 << self.pin_number) == 0 } } #[inline(always)] @@ -102,7 +102,7 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr.read().bits() & (1 << self.pin_number) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << self.pin_number) == 0 } } } @@ -115,6 +115,6 @@ impl PartiallyErasedPin> { #[inline(always)] pub fn is_low(&self) -> bool { // NOTE(unsafe) atomic read with no side effects - unsafe { (*Gpio::

::ptr()).idr.read().bits() & (1 << self.pin_number) == 0 } + unsafe { (*Gpio::

::ptr()).idr().read().bits() & (1 << self.pin_number) == 0 } } } diff --git a/src/i2c.rs b/src/i2c.rs index 51948159..b3cb8b22 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -226,25 +226,25 @@ impl I2c { let pclk1_mhz = self.pclk1.to_MHz() as u16; self.i2c - .cr2 + .cr2() .write(|w| unsafe { w.freq().bits(pclk1_mhz as u8) }); - self.i2c.cr1.write(|w| w.pe().clear_bit()); + self.i2c.cr1().write(|w| w.pe().clear_bit()); match self.mode { Mode::Standard { .. } => { self.i2c - .trise - .write(|w| w.trise().bits((pclk1_mhz + 1) as u8)); + .trise() + .write(|w| w.trise().set((pclk1_mhz + 1) as u8)); self.i2c - .ccr + .ccr() .write(|w| unsafe { w.ccr().bits(((self.pclk1 / (freq * 2)) as u16).max(4)) }); } Mode::Fast { ref duty_cycle, .. } => { self.i2c - .trise - .write(|w| w.trise().bits((pclk1_mhz * 300 / 1000 + 1) as u8)); + .trise() + .write(|w| w.trise().set((pclk1_mhz * 300 / 1000 + 1) as u8)); - self.i2c.ccr.write(|w| { + self.i2c.ccr().write(|w| { let (freq, duty) = match duty_cycle { DutyCycle::Ratio2to1 => (((self.pclk1 / (freq * 3)) as u16).max(1), false), DutyCycle::Ratio16to9 => (((self.pclk1 / (freq * 25)) as u16).max(1), true), @@ -255,32 +255,32 @@ impl I2c { } }; - self.i2c.cr1.modify(|_, w| w.pe().set_bit()); + self.i2c.cr1().modify(|_, w| w.pe().set_bit()); } /// Perform an I2C software reset fn reset(&mut self) { - self.i2c.cr1.write(|w| w.pe().set_bit().swrst().set_bit()); - self.i2c.cr1.reset(); + self.i2c.cr1().write(|w| w.pe().set_bit().swrst().set_bit()); + self.i2c.cr1().reset(); self.init(); } /// Generate START condition fn send_start(&mut self) { - self.i2c.cr1.modify(|_, w| w.start().set_bit()); + self.i2c.cr1().modify(|_, w| w.start().set_bit()); } /// Sends the (7-Bit) address on the I2C bus. The 8th bit on the bus is set /// depending on wether it is a read or write transfer. fn send_addr(&self, addr: u8, read: bool) { self.i2c - .dr - .write(|w| w.dr().bits(addr << 1 | (u8::from(read)))); + .dr() + .write(|w| w.dr().set(addr << 1 | (u8::from(read)))); } /// Generate STOP condition fn send_stop(&self) { - self.i2c.cr1.modify(|_, w| w.stop().set_bit()); + self.i2c.cr1().modify(|_, w| w.stop().set_bit()); } /// Releases the I2C peripheral and associated pins diff --git a/src/i2c/blocking.rs b/src/i2c/blocking.rs index af8ba7f7..315adec1 100644 --- a/src/i2c/blocking.rs +++ b/src/i2c/blocking.rs @@ -77,19 +77,19 @@ impl I2c { macro_rules! wait_for_flag { ($i2c:expr, $flag:ident, $nack:ident) => {{ - let sr1 = $i2c.sr1.read(); + let sr1 = $i2c.sr1().read(); if sr1.berr().bit_is_set() { - $i2c.sr1.write(|w| w.berr().clear_bit()); + $i2c.sr1().write(|w| w.berr().clear_bit()); Err(Error::Bus.into()) } else if sr1.arlo().bit_is_set() { - $i2c.sr1.write(|w| w.arlo().clear_bit()); + $i2c.sr1().write(|w| w.arlo().clear_bit()); Err(Error::ArbitrationLoss.into()) } else if sr1.af().bit_is_set() { - $i2c.sr1.write(|w| w.af().clear_bit()); + $i2c.sr1().write(|w| w.af().clear_bit()); Err(Error::NoAcknowledge(NoAcknowledgeSource::$nack).into()) } else if sr1.ovr().bit_is_set() { - $i2c.sr1.write(|w| w.ovr().clear_bit()); + $i2c.sr1().write(|w| w.ovr().clear_bit()); Err(Error::Overrun.into()) } else if sr1.$flag().bit_is_set() { Ok(()) @@ -138,7 +138,7 @@ impl BlockingI2c { /// method returns `WouldBlock` so the program can act accordingly /// (busy wait, async, ...) fn wait_for_stop(&mut self) -> nb::Result<(), Error> { - if self.nb.i2c.cr1.read().stop().is_no_stop() { + if self.nb.i2c.cr1().read().stop().is_no_stop() { Ok(()) } else { Err(nb::Error::WouldBlock) @@ -164,7 +164,7 @@ impl BlockingI2c { } fn send_addr_and_wait(&mut self, addr: u8, read: bool) -> Result<(), Error> { - self.nb.i2c.sr1.read(); + self.nb.i2c.sr1().read(); self.nb.send_addr(addr, read); let ret = busy_wait_cycles!( wait_for_flag!(self.nb.i2c, addr, Address), @@ -177,14 +177,14 @@ impl BlockingI2c { } fn write_bytes_and_wait(&mut self, bytes: &[u8]) -> Result<(), Error> { - self.nb.i2c.sr1.read(); - self.nb.i2c.sr2.read(); + self.nb.i2c.sr1().read(); + self.nb.i2c.sr2().read(); - self.nb.i2c.dr.write(|w| w.dr().bits(bytes[0])); + self.nb.i2c.dr().write(|w| w.dr().set(bytes[0])); for byte in &bytes[1..] { busy_wait_cycles!(wait_for_flag!(self.nb.i2c, tx_e, Data), self.timeouts.data)?; - self.nb.i2c.dr.write(|w| w.dr().bits(*byte)); + self.nb.i2c.dr().write(|w| w.dr().set(*byte)); } busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btf, Data), self.timeouts.data)?; @@ -216,42 +216,42 @@ impl BlockingI2c { match buffer.len() { 1 => { - self.nb.i2c.cr1.modify(|_, w| w.ack().clear_bit()); - self.nb.i2c.sr1.read(); - self.nb.i2c.sr2.read(); + self.nb.i2c.cr1().modify(|_, w| w.ack().clear_bit()); + self.nb.i2c.sr1().read(); + self.nb.i2c.sr2().read(); self.nb.send_stop(); busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rx_ne, Data), self.timeouts.data)?; - buffer[0] = self.nb.i2c.dr.read().dr().bits(); + buffer[0] = self.nb.i2c.dr().read().dr().bits(); busy_wait_cycles!(self.wait_for_stop(), self.timeouts.data)?; - self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit()); + self.nb.i2c.cr1().modify(|_, w| w.ack().set_bit()); } 2 => { self.nb .i2c - .cr1 + .cr1() .modify(|_, w| w.pos().set_bit().ack().set_bit()); - self.nb.i2c.sr1.read(); - self.nb.i2c.sr2.read(); - self.nb.i2c.cr1.modify(|_, w| w.ack().clear_bit()); + self.nb.i2c.sr1().read(); + self.nb.i2c.sr2().read(); + self.nb.i2c.cr1().modify(|_, w| w.ack().clear_bit()); busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btf, Data), self.timeouts.data)?; self.nb.send_stop(); - buffer[0] = self.nb.i2c.dr.read().dr().bits(); - buffer[1] = self.nb.i2c.dr.read().dr().bits(); + buffer[0] = self.nb.i2c.dr().read().dr().bits(); + buffer[1] = self.nb.i2c.dr().read().dr().bits(); busy_wait_cycles!(self.wait_for_stop(), self.timeouts.data)?; self.nb .i2c - .cr1 + .cr1() .modify(|_, w| w.pos().clear_bit().ack().clear_bit()); - self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit()); + self.nb.i2c.cr1().modify(|_, w| w.ack().set_bit()); } buffer_len => { - self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit()); - self.nb.i2c.sr1.read(); - self.nb.i2c.sr2.read(); + self.nb.i2c.cr1().modify(|_, w| w.ack().set_bit()); + self.nb.i2c.sr1().read(); + self.nb.i2c.sr2().read(); let (first_bytes, last_two_bytes) = buffer.split_at_mut(buffer_len - 3); for byte in first_bytes { @@ -259,19 +259,19 @@ impl BlockingI2c { wait_for_flag!(self.nb.i2c, rx_ne, Data), self.timeouts.data )?; - *byte = self.nb.i2c.dr.read().dr().bits(); + *byte = self.nb.i2c.dr().read().dr().bits(); } busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btf, Data), self.timeouts.data)?; - self.nb.i2c.cr1.modify(|_, w| w.ack().clear_bit()); - last_two_bytes[0] = self.nb.i2c.dr.read().dr().bits(); + self.nb.i2c.cr1().modify(|_, w| w.ack().clear_bit()); + last_two_bytes[0] = self.nb.i2c.dr().read().dr().bits(); self.nb.send_stop(); - last_two_bytes[1] = self.nb.i2c.dr.read().dr().bits(); + last_two_bytes[1] = self.nb.i2c.dr().read().dr().bits(); busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rx_ne, Data), self.timeouts.data)?; - last_two_bytes[2] = self.nb.i2c.dr.read().dr().bits(); + last_two_bytes[2] = self.nb.i2c.dr().read().dr().bits(); busy_wait_cycles!(self.wait_for_stop(), self.timeouts.data)?; - self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit()); + self.nb.i2c.cr1().modify(|_, w| w.ack().set_bit()); } } diff --git a/src/qei.rs b/src/qei.rs index bf7af2a3..dd2a708b 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -153,7 +153,7 @@ macro_rules! hal { tim.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2()); // enable and configure to capture on rising edge - tim.ccer.write(|w| { + tim.ccer().write(|w| { w.cc1e() .set_bit() .cc1p() @@ -165,10 +165,10 @@ macro_rules! hal { }); // configure as quadrature encoder - tim.smcr.write(|w| w.sms().bits(options.slave_mode as u8)); + tim.smcr().write(|w| w.sms().set(options.slave_mode as u8)); - tim.arr.write(|w| w.arr().bits(options.auto_reload_value)); - tim.cr1.write(|w| w.cen().set_bit()); + tim.arr().write(|w| w.arr().set(options.auto_reload_value)); + tim.cr1().write(|w| w.cen().set_bit()); Qei { tim, pins, _remap: PhantomData } } @@ -182,11 +182,11 @@ macro_rules! hal { type Count = u16; fn count(&self) -> u16 { - self.tim.cnt.read().cnt().bits() + self.tim.cnt().read().cnt().bits() } fn direction(&self) -> Direction { - if self.tim.cr1.read().dir().bit_is_clear() { + if self.tim.cr1().read().dir().bit_is_clear() { Direction::Upcounting } else { Direction::Downcounting diff --git a/src/rcc.rs b/src/rcc.rs index 2f583335..cd970b4a 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -55,7 +55,7 @@ pub struct AHB { impl AHB { fn enr(rcc: &rcc::RegisterBlock) -> &rcc::AHBENR { - &rcc.ahbenr + rcc.ahbenr() } } @@ -66,11 +66,11 @@ pub struct APB1 { impl APB1 { fn enr(rcc: &rcc::RegisterBlock) -> &rcc::APB1ENR { - &rcc.apb1enr + rcc.apb1enr() } fn rstr(rcc: &rcc::RegisterBlock) -> &rcc::APB1RSTR { - &rcc.apb1rstr + rcc.apb1rstr() } } @@ -89,11 +89,11 @@ pub struct APB2 { impl APB2 { fn enr(rcc: &rcc::RegisterBlock) -> &rcc::APB2ENR { - &rcc.apb2enr + rcc.apb2enr() } fn rstr(rcc: &rcc::RegisterBlock) -> &rcc::APB2RSTR { - &rcc.apb2rstr + rcc.apb2rstr() } } @@ -224,32 +224,32 @@ impl CFGR { if cfg.hse.is_some() { // enable HSE and wait for it to be ready - rcc.cr.modify(|_, w| { + rcc.cr().modify(|_, w| { if cfg.hse_bypass { w.hsebyp().bypassed(); } w.hseon().set_bit() }); - while rcc.cr.read().hserdy().bit_is_clear() {} + while rcc.cr().read().hserdy().bit_is_clear() {} } if let Some(pllmul_bits) = cfg.pllmul { // enable PLL and wait for it to be ready #[allow(unused_unsafe)] - rcc.cfgr.modify(|_, w| unsafe { + rcc.cfgr().modify(|_, w| unsafe { w.pllmul().bits(pllmul_bits).pllsrc().bit(cfg.hse.is_some()) }); - rcc.cr.modify(|_, w| w.pllon().set_bit()); + rcc.cr().modify(|_, w| w.pllon().set_bit()); - while rcc.cr.read().pllrdy().bit_is_clear() {} + while rcc.cr().read().pllrdy().bit_is_clear() {} } // set prescalers and clock source #[cfg(feature = "connectivity")] - rcc.cfgr.modify(|_, w| unsafe { + rcc.cfgr().modify(|_, w| unsafe { w.adcpre().variant(cfg.adcpre); w.ppre2() .bits(cfg.ppre2 as u8) @@ -273,7 +273,7 @@ impl CFGR { }); #[cfg(feature = "stm32f103")] - rcc.cfgr.modify(|_, w| unsafe { + rcc.cfgr().modify(|_, w| unsafe { w.adcpre().variant(cfg.adcpre); w.ppre2() .bits(cfg.ppre2 as u8) @@ -294,7 +294,7 @@ impl CFGR { }); #[cfg(any(feature = "stm32f100", feature = "stm32f101"))] - rcc.cfgr.modify(|_, w| unsafe { + rcc.cfgr().modify(|_, w| unsafe { w.adcpre().variant(cfg.adcpre); w.ppre2() .bits(cfg.ppre2 as u8) @@ -332,7 +332,7 @@ impl BKP { crate::pac::PWR::enable(rcc); // Enable access to the backup registers - pwr.cr.modify(|_r, w| w.dbp().set_bit()); + pwr.cr().modify(|_r, w| w.dbp().set_bit()); BackupDomain { _regs: bkp } } @@ -520,7 +520,7 @@ impl Default for Config { ppre1: PPre::Div1, ppre2: PPre::Div1, #[cfg(any(feature = "stm32f103", feature = "connectivity"))] - usbpre: UsbPre::Div15, + usbpre: UsbPre::Div1_5, adcpre: AdcPre::Div2, allow_overclock: false, } @@ -566,10 +566,10 @@ pub enum PPre { } #[cfg(feature = "stm32f103")] -pub type UsbPre = rcc::cfgr::USBPRE_A; +pub type UsbPre = rcc::cfgr::USBPRE; #[cfg(feature = "connectivity")] -pub type UsbPre = rcc::cfgr::OTGFSPRE_A; -pub type AdcPre = rcc::cfgr::ADCPRE_A; +pub type UsbPre = rcc::cfgr::OTGFSPRE; +pub type AdcPre = rcc::cfgr::ADCPRE; impl Config { pub const fn from_cfgr(cfgr: CFGR) -> Self { @@ -658,7 +658,7 @@ impl Config { // usbpre == false: divide clock by 1.5, otherwise no division #[cfg(any(feature = "stm32f103", feature = "connectivity"))] let usbpre = match (hse, pllmul_bits, sysclk) { - (Some(_), Some(_), 72_000_000) => UsbPre::Div15, + (Some(_), Some(_), 72_000_000) => UsbPre::Div1_5, _ => UsbPre::Div1, }; diff --git a/src/rtc.rs b/src/rtc.rs index 292fd0f3..ff177a33 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -75,8 +75,10 @@ impl Rtc { let prl = LSE_HERTZ.raw() - 1; assert!(prl < 1 << 20); result.perform_write(|s| { - s.regs.prlh.write(|w| unsafe { w.bits(prl >> 16) }); - s.regs.prll.write(|w| unsafe { w.bits(prl as u16 as u32) }); + s.regs.prlh().write(|w| unsafe { w.bits(prl >> 16) }); + s.regs + .prll() + .write(|w| unsafe { w.bits(prl as u16 as u32) }); }); result @@ -110,7 +112,8 @@ impl Rtc { /// Returns whether the RTC is currently enabled and LSE is selected. fn is_enabled() -> bool { let rcc = unsafe { &*RCC::ptr() }; - rcc.bdcr.read().rtcen().bit() && rcc.bdcr.read().rtcsel().is_lse() + let bdcr = rcc.bdcr().read(); + bdcr.rtcen().is_enabled() && bdcr.rtcsel().is_lse() } /// Enables the RTC device with the lse as the clock @@ -118,17 +121,13 @@ impl Rtc { // NOTE: Safe RCC access because we are only accessing bdcr // and we have a &mut on BackupDomain let rcc = unsafe { &*RCC::ptr() }; - rcc.bdcr.modify(|_, w| { - w - // start the LSE oscillator - .lseon() - .set_bit() - // Enable the RTC - .rtcen() - .set_bit() - // Set the source of the RTC to LSE - .rtcsel() - .lse() + rcc.bdcr().modify(|_, w| { + // start the LSE oscillator + w.lseon().set_bit(); + // Enable the RTC + w.rtcen().set_bit(); + // Set the source of the RTC to LSE + w.rtcsel().lse() }) } } @@ -161,8 +160,10 @@ impl Rtc { let prl = LSI_HERTZ.raw() - 1; assert!(prl < 1 << 20); result.perform_write(|s| { - s.regs.prlh.write(|w| unsafe { w.bits(prl >> 16) }); - s.regs.prll.write(|w| unsafe { w.bits(prl as u16 as u32) }); + s.regs.prlh().write(|w| unsafe { w.bits(prl >> 16) }); + s.regs + .prll() + .write(|w| unsafe { w.bits(prl as u16 as u32) }); }); result @@ -184,7 +185,7 @@ impl Rtc { /// Returns whether the RTC is currently enabled and LSI is selected. fn is_enabled() -> bool { let rcc = unsafe { &*RCC::ptr() }; - rcc.bdcr.read().rtcen().bit() && rcc.bdcr.read().rtcsel().is_lsi() + rcc.bdcr().read().rtcen().bit() && rcc.bdcr().read().rtcsel().is_lsi() } /// Enables the RTC device with the lsi as the clock @@ -192,20 +193,15 @@ impl Rtc { // NOTE: Safe RCC access because we are only accessing bdcr // and we have a &mut on BackupDomain let rcc = unsafe { &*RCC::ptr() }; - rcc.csr.modify(|_, w| { - w - // start the LSI oscillator - .lsion() - .set_bit() + rcc.csr().modify(|_, w| { + // start the LSI oscillator + w.lsion().set_bit() }); - rcc.bdcr.modify(|_, w| { - w - // Enable the RTC - .rtcen() - .set_bit() - // Set the source of the RTC to LSI - .rtcsel() - .lsi() + rcc.bdcr().modify(|_, w| { + // Enable the RTC + w.rtcen().set_bit(); + // Set the source of the RTC to LSI + w.rtcsel().lsi() }) } } @@ -239,8 +235,10 @@ impl Rtc { let prl = hse.raw() / 128 - 1; assert!(prl < 1 << 20); result.perform_write(|s| { - s.regs.prlh.write(|w| unsafe { w.bits(prl >> 16) }); - s.regs.prll.write(|w| unsafe { w.bits(prl as u16 as u32) }); + s.regs.prlh().write(|w| unsafe { w.bits(prl >> 16) }); + s.regs + .prll() + .write(|w| unsafe { w.bits(prl as u16 as u32) }); }); result @@ -265,7 +263,8 @@ impl Rtc { fn is_enabled() -> bool { let rcc = unsafe { &*RCC::ptr() }; - rcc.bdcr.read().rtcen().bit() && rcc.bdcr.read().rtcsel().is_hse() + let bdcr = rcc.bdcr().read(); + bdcr.rtcen().is_enabled() && bdcr.rtcsel().is_hse() } /// Enables the RTC device with the lsi as the clock @@ -273,17 +272,14 @@ impl Rtc { // NOTE: Safe RCC access because we are only accessing bdcr // and we have a &mut on BackupDomain let rcc = unsafe { &*RCC::ptr() }; - if rcc.cr.read().hserdy().bit_is_clear() { + if rcc.cr().read().hserdy().bit_is_clear() { panic!("HSE oscillator not ready"); } - rcc.bdcr.modify(|_, w| { - w - // Enable the RTC - .rtcen() - .set_bit() - // Set the source of the RTC to HSE/128 - .rtcsel() - .hse() + rcc.bdcr().modify(|_, w| { + // Enable the RTC + w.rtcen().set_bit(); + // Set the source of the RTC to HSE/128 + w.rtcsel().hse() }) } } @@ -298,9 +294,9 @@ impl Rtc { let prescaler = LSE_HERTZ / frequency - 1; self.perform_write(|s| { - s.regs.prlh.write(|w| unsafe { w.bits(prescaler >> 16) }); + s.regs.prlh().write(|w| unsafe { w.bits(prescaler >> 16) }); s.regs - .prll + .prll() .write(|w| unsafe { w.bits(prescaler as u16 as u32) }); }); } @@ -309,10 +305,10 @@ impl Rtc { pub fn set_time(&mut self, counter_value: u32) { self.perform_write(|s| { s.regs - .cnth + .cnth() .write(|w| unsafe { w.bits(counter_value >> 16) }); s.regs - .cntl + .cntl() .write(|w| unsafe { w.bits(counter_value as u16 as u32) }); }); } @@ -331,10 +327,10 @@ impl Rtc { #[allow(unused_unsafe)] self.perform_write(|s| { s.regs - .alrh + .alrh() .write(|w| unsafe { w.alrh().bits((alarm_value >> 16) as u16) }); s.regs - .alrl + .alrl() .write(|w| unsafe { w.alrl().bits(alarm_value as u16) }); }); @@ -347,7 +343,7 @@ impl Rtc { pub fn listen_alarm(&mut self) { // Enable alarm interrupt self.perform_write(|s| { - s.regs.crh.modify(|_, w| w.alrie().set_bit()); + s.regs.crh().modify(|_, w| w.alrie().set_bit()); }) } @@ -355,36 +351,36 @@ impl Rtc { pub fn unlisten_alarm(&mut self) { // Disable alarm interrupt self.perform_write(|s| { - s.regs.crh.modify(|_, w| w.alrie().clear_bit()); + s.regs.crh().modify(|_, w| w.alrie().clear_bit()); }) } /// Reads the current counter pub fn current_time(&self) -> u32 { // Wait for the APB1 interface to be ready - while !self.regs.crl.read().rsf().bit() {} + while !self.regs.crl().read().rsf().bit() {} - self.regs.cnth.read().bits() << 16 | self.regs.cntl.read().bits() + self.regs.cnth().read().bits() << 16 | self.regs.cntl().read().bits() } /// Enables triggering the RTC interrupt every time the RTC counter is increased pub fn listen_seconds(&mut self) { - self.perform_write(|s| s.regs.crh.modify(|_, w| w.secie().set_bit())) + self.perform_write(|s| s.regs.crh().modify(|_, w| w.secie().set_bit())) } /// Disables the RTC second interrupt pub fn unlisten_seconds(&mut self) { - self.perform_write(|s| s.regs.crh.modify(|_, w| w.secie().clear_bit())) + self.perform_write(|s| s.regs.crh().modify(|_, w| w.secie().clear_bit())) } /// Clears the RTC second interrupt flag pub fn clear_second_flag(&mut self) { - self.perform_write(|s| s.regs.crl.modify(|_, w| w.secf().clear_bit())) + self.perform_write(|s| s.regs.crl().modify(|_, w| w.secf().clear_bit())) } /// Clears the RTC alarm interrupt flag pub fn clear_alarm_flag(&mut self) { - self.perform_write(|s| s.regs.crl.modify(|_, w| w.alrf().clear_bit())) + self.perform_write(|s| s.regs.crl().modify(|_, w| w.alrf().clear_bit())) } /** @@ -399,8 +395,8 @@ impl Rtc { ``` */ pub fn wait_alarm(&mut self) -> nb::Result<(), Infallible> { - if self.regs.crl.read().alrf().bit() { - self.regs.crl.modify(|_, w| w.alrf().clear_bit()); + if self.regs.crl().read().alrf().bit() { + self.regs.crl().modify(|_, w| w.alrf().clear_bit()); Ok(()) } else { Err(nb::Error::WouldBlock) @@ -414,16 +410,16 @@ impl Rtc { */ fn perform_write(&mut self, func: impl Fn(&mut Self)) { // Wait for the last write operation to be done - while !self.regs.crl.read().rtoff().bit() {} + while !self.regs.crl().read().rtoff().bit() {} // Put the clock into config mode - self.regs.crl.modify(|_, w| w.cnf().set_bit()); + self.regs.crl().modify(|_, w| w.cnf().set_bit()); // Perform the write operation func(self); // Take the device out of config mode - self.regs.crl.modify(|_, w| w.cnf().clear_bit()); + self.regs.crl().modify(|_, w| w.cnf().clear_bit()); // Wait for the write to be done - while !self.regs.crl.read().rtoff().bit() {} + while !self.regs.crl().read().rtoff().bit() {} } } diff --git a/src/serial.rs b/src/serial.rs index 27594d77..0463ed71 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -400,7 +400,7 @@ impl Serial { // UE: enable USART // TE: enable transceiver // RE: enable receiver - usart.cr1.modify(|_r, w| { + usart.cr1().modify(|_r, w| { w.ue().set_bit(); w.te().set_bit(); w.re().set_bit(); @@ -472,18 +472,18 @@ fn apply_config(config: Config, clocks: &Clocks) { // Configure baud rate let brr = USART::clock(clocks).raw() / config.baudrate.0; assert!(brr >= 16, "impossible baud rate"); - usart.brr.write(|w| unsafe { w.bits(brr) }); + usart.brr().write(|w| unsafe { w.bits(brr) }); // Configure word - usart.cr1.modify(|_r, w| { + usart.cr1().modify(|_r, w| { w.m().bit(match config.wordlength { WordLength::Bits8 => false, WordLength::Bits9 => true, }); - use crate::pac::usart1::cr1::PS_A; + use crate::pac::usart1::cr1::PS; w.ps().variant(match config.parity { - Parity::ParityOdd => PS_A::Odd, - _ => PS_A::Even, + Parity::ParityOdd => PS::Odd, + _ => PS::Even, }); w.pce().bit(!matches!(config.parity, Parity::ParityNone)); w @@ -496,7 +496,7 @@ fn apply_config(config: Config, clocks: &Clocks) { StopBits::STOP2 => 0b10, StopBits::STOP1P5 => 0b11, }; - usart.cr2.modify(|_r, w| w.stop().bits(stop_bits)); + usart.cr2().modify(|_r, w| w.stop().set(stop_bits)); } /// Reconfigure the USART instance. @@ -527,8 +527,8 @@ impl Tx { pub fn write_u16(&mut self, word: u16) -> nb::Result<(), Error> { let usart = unsafe { &*USART::ptr() }; - if usart.sr.read().txe().bit_is_set() { - usart.dr.write(|w| w.dr().bits(word)); + if usart.sr().read().txe().bit_is_set() { + usart.dr().write(|w| w.dr().set(word)); Ok(()) } else { Err(nb::Error::WouldBlock) @@ -556,7 +556,7 @@ impl Tx { pub fn flush(&mut self) -> nb::Result<(), Error> { let usart = unsafe { &*USART::ptr() }; - if usart.sr.read().tc().bit_is_set() { + if usart.sr().read().tc().bit_is_set() { Ok(()) } else { Err(nb::Error::WouldBlock) @@ -569,21 +569,21 @@ impl Tx { /// Start listening for transmit interrupt event pub fn listen(&mut self) { - unsafe { (*USART::ptr()).cr1.modify(|_, w| w.txeie().set_bit()) }; + unsafe { (*USART::ptr()).cr1().modify(|_, w| w.txeie().set_bit()) }; } /// Stop listening for transmit interrupt event pub fn unlisten(&mut self) { - unsafe { (*USART::ptr()).cr1.modify(|_, w| w.txeie().clear_bit()) }; + unsafe { (*USART::ptr()).cr1().modify(|_, w| w.txeie().clear_bit()) }; } /// Returns true if the tx register is empty (and can accept data) pub fn is_tx_empty(&self) -> bool { - unsafe { (*USART::ptr()).sr.read().txe().bit_is_set() } + unsafe { (*USART::ptr()).sr().read().txe().bit_is_set() } } pub fn is_tx_complete(&self) -> bool { - unsafe { (*USART::ptr()).sr.read().tc().bit_is_set() } + unsafe { (*USART::ptr()).sr().read().tc().bit_is_set() } } } @@ -603,7 +603,7 @@ impl Rx { /// 8 received data bits and all other bits set to zero. pub fn read_u16(&mut self) -> nb::Result { let usart = unsafe { &*USART::ptr() }; - let sr = usart.sr.read(); + let sr = usart.sr().read(); // Check for any errors let err = if sr.pe().bit_is_set() { @@ -621,14 +621,14 @@ impl Rx { if let Some(err) = err { // Some error occurred. In order to clear that error flag, you have to // do a read from the sr register followed by a read from the dr register. - let _ = usart.sr.read(); - let _ = usart.dr.read(); + let _ = usart.sr().read(); + let _ = usart.dr().read(); Err(nb::Error::Other(err)) } else { // Check if a byte is available if sr.rxne().bit_is_set() { // Read the received byte - Ok(usart.dr.read().dr().bits()) + Ok(usart.dr().read().dr().bits()) } else { Err(nb::Error::WouldBlock) } @@ -641,39 +641,39 @@ impl Rx { /// Start listening for receive interrupt event pub fn listen(&mut self) { - unsafe { (*USART::ptr()).cr1.modify(|_, w| w.rxneie().set_bit()) }; + unsafe { (*USART::ptr()).cr1().modify(|_, w| w.rxneie().set_bit()) }; } /// Stop listening for receive interrupt event pub fn unlisten(&mut self) { - unsafe { (*USART::ptr()).cr1.modify(|_, w| w.rxneie().clear_bit()) }; + unsafe { (*USART::ptr()).cr1().modify(|_, w| w.rxneie().clear_bit()) }; } /// Start listening for idle interrupt event pub fn listen_idle(&mut self) { - unsafe { (*USART::ptr()).cr1.modify(|_, w| w.idleie().set_bit()) }; + unsafe { (*USART::ptr()).cr1().modify(|_, w| w.idleie().set_bit()) }; } /// Stop listening for idle interrupt event pub fn unlisten_idle(&mut self) { - unsafe { (*USART::ptr()).cr1.modify(|_, w| w.idleie().clear_bit()) }; + unsafe { (*USART::ptr()).cr1().modify(|_, w| w.idleie().clear_bit()) }; } /// Returns true if the line idle status is set pub fn is_idle(&self) -> bool { - unsafe { (*USART::ptr()).sr.read().idle().bit_is_set() } + unsafe { (*USART::ptr()).sr().read().idle().bit_is_set() } } /// Returns true if the rx register is not empty (and can be read) pub fn is_rx_not_empty(&self) -> bool { - unsafe { (*USART::ptr()).sr.read().rxne().bit_is_set() } + unsafe { (*USART::ptr()).sr().read().rxne().bit_is_set() } } /// Clear idle line interrupt flag pub fn clear_idle_interrupt(&self) { unsafe { - let _ = (*USART::ptr()).sr.read(); - let _ = (*USART::ptr()).dr.read(); + let _ = (*USART::ptr()).sr().read(); + let _ = (*USART::ptr()).dr().read(); } } } @@ -789,7 +789,7 @@ macro_rules! serialdma { impl Rx<$USARTX> { pub fn with_dma(self, channel: $dmarxch) -> $rxdma { unsafe { - (*$USARTX::ptr()).cr3.modify(|_, w| w.dmar().set_bit()); + (*$USARTX::ptr()).cr3().modify(|_, w| w.dmar().set_bit()); } RxDma { payload: self, @@ -801,7 +801,7 @@ macro_rules! serialdma { impl Tx<$USARTX> { pub fn with_dma(self, channel: $dmatxch) -> $txdma { unsafe { - (*$USARTX::ptr()).cr3.modify(|_, w| w.dmat().set_bit()); + (*$USARTX::ptr()).cr3().modify(|_, w| w.dmat().set_bit()); } TxDma { payload: self, @@ -814,7 +814,7 @@ macro_rules! serialdma { pub fn release(mut self) -> (Rx<$USARTX>, $dmarxch) { self.stop(); unsafe { - (*$USARTX::ptr()).cr3.modify(|_, w| w.dmar().clear_bit()); + (*$USARTX::ptr()).cr3().modify(|_, w| w.dmar().clear_bit()); } let RxDma { payload, channel } = self; (payload, channel) @@ -825,7 +825,7 @@ macro_rules! serialdma { pub fn release(mut self) -> (Tx<$USARTX>, $dmatxch) { self.stop(); unsafe { - (*$USARTX::ptr()).cr3.modify(|_, w| w.dmat().clear_bit()); + (*$USARTX::ptr()).cr3().modify(|_, w| w.dmat().clear_bit()); } let TxDma { payload, channel } = self; (payload, channel) @@ -841,14 +841,16 @@ macro_rules! serialdma { // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it // until the end of the transfer. let (ptr, len) = unsafe { buffer.write_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*$USARTX::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*$USARTX::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { w.mem2mem().clear_bit(); w.pl().medium(); w.msize().bits8(); @@ -871,13 +873,15 @@ macro_rules! serialdma { // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it // until the end of the transfer. let (ptr, len) = unsafe { buffer.write_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*$USARTX::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*$USARTX::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { w.mem2mem().clear_bit(); w.pl().medium(); w.msize().bits8(); @@ -900,15 +904,17 @@ macro_rules! serialdma { // until the end of the transfer. let (ptr, len) = unsafe { buffer.read_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*$USARTX::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*$USARTX::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { w.mem2mem().clear_bit(); w.pl().medium(); w.msize().bits8(); diff --git a/src/spi.rs b/src/spi.rs index ae9ab445..95a9707e 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -444,7 +444,7 @@ impl Spi { SPI::reset(rcc); // disable SS output - spi.cr2.write(|w| w.ssoe().clear_bit()); + spi.cr2().write(|w| w.ssoe().clear_bit()); let br = match SPI::clock(clocks) / freq { 0 => unreachable!(), @@ -460,7 +460,7 @@ impl Spi { let pins = pins.into(); - spi.cr1.write(|w| { + spi.cr1().write(|w| { // clock phase from config w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition); // clock polarity from config @@ -468,7 +468,7 @@ impl Spi { // mstr: master configuration w.mstr().set_bit(); // baudrate value - w.br().bits(br); + w.br().set(br); // lsbfirst: MSB first w.lsbfirst().clear_bit(); // ssm: enable software slave management (NSS pin free for other uses) @@ -511,11 +511,11 @@ impl SpiSlave { SPI::reset(rcc); // disable SS output - spi.cr2.write(|w| w.ssoe().clear_bit()); + spi.cr2().write(|w| w.ssoe().clear_bit()); let pins = pins.into(); - spi.cr1.write(|w| { + spi.cr1().write(|w| { // clock phase from config w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition); // clock polarity from config @@ -559,12 +559,12 @@ impl SpiReadWrite for SpiInner { fn read_data_reg(&mut self) -> W { // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows // reading a half-word) - unsafe { ptr::read_volatile(ptr::addr_of!(self.spi.dr) as *const W) } + unsafe { ptr::read_volatile(self.spi.dr().as_ptr() as *const W) } } fn write_data_reg(&mut self, data: W) { // NOTE(write_volatile) see note above - unsafe { ptr::write_volatile(ptr::addr_of!(self.spi.dr) as *mut W, data) } + unsafe { ptr::write_volatile(self.spi.dr().as_ptr() as *mut W, data) } } // Implement write as per the "Transmit only procedure" page 712 @@ -575,7 +575,7 @@ impl SpiReadWrite for SpiInner { // Write each word when the tx buffer is empty for word in words { loop { - let sr = self.spi.sr.read(); + let sr = self.spi.sr().read(); if sr.txe().bit_is_set() { self.write_data_reg(*word); if sr.modf().bit_is_set() { @@ -591,7 +591,7 @@ impl SpiReadWrite for SpiInner { while self.is_busy() {} // Clear OVR set due to dropped received values let _ = self.read_data_reg(); - let _ = self.spi.sr.read(); + let _ = self.spi.sr().read(); Ok(()) } } @@ -599,65 +599,64 @@ impl SpiReadWrite for SpiInner { impl SpiInner { /// Select which frame format is used for data transfers pub fn bit_format(&mut self, format: SpiBitFormat) { - match format { - SpiBitFormat::LsbFirst => self.spi.cr1.modify(|_, w| w.lsbfirst().set_bit()), - SpiBitFormat::MsbFirst => self.spi.cr1.modify(|_, w| w.lsbfirst().clear_bit()), - } + self.spi + .cr1() + .modify(|_, w| w.lsbfirst().bit(matches!(format, SpiBitFormat::LsbFirst))); } /// Starts listening to the SPI by enabling the _Received data /// ready to be read (RXNE)_ interrupt and _Transmit data /// register empty (TXE)_ interrupt pub fn listen(&mut self, event: Event) { - match event { - Event::Rxne => self.spi.cr2.modify(|_, w| w.rxneie().set_bit()), - Event::Txe => self.spi.cr2.modify(|_, w| w.txeie().set_bit()), - Event::Error => self.spi.cr2.modify(|_, w| w.errie().set_bit()), - } + self.spi.cr2().modify(|_, w| match event { + Event::Rxne => w.rxneie().set_bit(), + Event::Txe => w.txeie().set_bit(), + Event::Error => w.errie().set_bit(), + }); } /// Stops listening to the SPI by disabling the _Received data /// ready to be read (RXNE)_ interrupt and _Transmit data /// register empty (TXE)_ interrupt pub fn unlisten(&mut self, event: Event) { - match event { - Event::Rxne => self.spi.cr2.modify(|_, w| w.rxneie().clear_bit()), - Event::Txe => self.spi.cr2.modify(|_, w| w.txeie().clear_bit()), - Event::Error => self.spi.cr2.modify(|_, w| w.errie().clear_bit()), - } + self.spi.cr2().modify(|_, w| match event { + Event::Rxne => w.rxneie().clear_bit(), + Event::Txe => w.txeie().clear_bit(), + Event::Error => w.errie().clear_bit(), + }); } /// Returns true if the tx register is empty (and can accept data) #[inline] pub fn is_tx_empty(&self) -> bool { - self.spi.sr.read().txe().bit_is_set() + self.spi.sr().read().txe().bit_is_set() } /// Returns true if the rx register is not empty (and can be read) #[inline] pub fn is_rx_not_empty(&self) -> bool { - self.spi.sr.read().rxne().bit_is_set() + self.spi.sr().read().rxne().bit_is_set() } /// Returns true if the transfer is in progress #[inline] pub fn is_busy(&self) -> bool { - self.spi.sr.read().bsy().bit_is_set() + self.spi.sr().read().bsy().bit_is_set() } /// Returns true if data are received and the previous data have not yet been read from SPI_DR. #[inline] pub fn is_overrun(&self) -> bool { - self.spi.sr.read().ovr().bit_is_set() + self.spi.sr().read().ovr().bit_is_set() } } impl Spi { /// Converts from 8bit dataframe to 16bit. pub fn frame_size_16bit(self) -> Spi { - self.spi.cr1.modify(|_, w| w.spe().clear_bit()); - self.spi.cr1.modify(|_, w| w.dff().set_bit()); - self.spi.cr1.modify(|_, w| w.spe().set_bit()); + self.spi.cr1().modify(|_, w| w.spe().clear_bit()); + self.spi.cr1().modify(|_, w| w.dff().set_bit()); + self.spi.cr1().modify(|_, w| w.spe().set_bit()); Spi { inner: SpiInner::new(self.inner.spi), pins: self.pins, @@ -668,9 +667,9 @@ impl Spi { impl SpiSlave { /// Converts from 8bit dataframe to 16bit. pub fn frame_size_16bit(self) -> SpiSlave { - self.spi.cr1.modify(|_, w| w.spe().clear_bit()); - self.spi.cr1.modify(|_, w| w.dff().set_bit()); - self.spi.cr1.modify(|_, w| w.spe().set_bit()); + self.spi.cr1().modify(|_, w| w.spe().clear_bit()); + self.spi.cr1().modify(|_, w| w.dff().set_bit()); + self.spi.cr1().modify(|_, w| w.spe().set_bit()); SpiSlave { inner: SpiInner::new(self.inner.spi), pins: self.pins, @@ -681,9 +680,9 @@ impl SpiSlave { impl Spi { /// Converts from 16bit dataframe to 8bit. pub fn frame_size_8bit(self) -> Spi { - self.spi.cr1.modify(|_, w| w.spe().clear_bit()); - self.spi.cr1.modify(|_, w| w.dff().clear_bit()); - self.spi.cr1.modify(|_, w| w.spe().set_bit()); + self.spi.cr1().modify(|_, w| w.spe().clear_bit()); + self.spi.cr1().modify(|_, w| w.dff().clear_bit()); + self.spi.cr1().modify(|_, w| w.spe().set_bit()); Spi { inner: SpiInner::new(self.inner.spi), pins: self.pins, @@ -694,9 +693,9 @@ impl Spi { impl SpiSlave { /// Converts from 16bit dataframe to 8bit. pub fn frame_size_8bit(self) -> SpiSlave { - self.spi.cr1.modify(|_, w| w.spe().clear_bit()); - self.spi.cr1.modify(|_, w| w.dff().clear_bit()); - self.spi.cr1.modify(|_, w| w.spe().set_bit()); + self.spi.cr1().modify(|_, w| w.spe().clear_bit()); + self.spi.cr1().modify(|_, w| w.dff().clear_bit()); + self.spi.cr1().modify(|_, w| w.spe().set_bit()); SpiSlave { inner: SpiInner::new(self.inner.spi), pins: self.pins, @@ -710,7 +709,7 @@ where W: Copy, { pub fn read_nonblocking(&mut self) -> nb::Result { - let sr = self.spi.sr.read(); + let sr = self.spi.sr().read(); Err(if sr.ovr().bit_is_set() { Error::Overrun.into() @@ -727,7 +726,7 @@ where }) } pub fn write_nonblocking(&mut self, data: W) -> nb::Result<(), Error> { - let sr = self.spi.sr.read(); + let sr = self.spi.sr().read(); // NOTE: Error::Overrun was deleted in #408. Need check Err(if sr.modf().bit_is_set() { @@ -789,14 +788,14 @@ macro_rules! spi_dma { impl Spi<$SPIi, u8, PULL> { pub fn with_tx_dma(self, channel: $TCi) -> SpiTxDma<$SPIi, $TCi, PULL> { - self.spi.cr2.modify(|_, w| w.txdmaen().set_bit()); + self.spi.cr2().modify(|_, w| w.txdmaen().set_bit()); SpiTxDma { payload: self, channel, } } pub fn with_rx_dma(self, channel: $RCi) -> SpiRxDma<$SPIi, $RCi, PULL> { - self.spi.cr2.modify(|_, w| w.rxdmaen().set_bit()); + self.spi.cr2().modify(|_, w| w.rxdmaen().set_bit()); SpiRxDma { payload: self, channel, @@ -808,7 +807,7 @@ macro_rules! spi_dma { txchannel: $TCi, ) -> SpiRxTxDma<$SPIi, $RCi, $TCi, PULL> { self.spi - .cr2 + .cr2() .modify(|_, w| w.rxdmaen().set_bit().txdmaen().set_bit()); SpiRxTxDma { payload: self, @@ -821,7 +820,7 @@ macro_rules! spi_dma { impl SpiTxDma<$SPIi, $TCi, PULL> { pub fn release(self) -> (Spi<$SPIi, u8, PULL>, $TCi) { let SpiTxDma { payload, channel } = self; - payload.spi.cr2.modify(|_, w| w.txdmaen().clear_bit()); + payload.spi.cr2().modify(|_, w| w.txdmaen().clear_bit()); (payload, channel) } } @@ -829,7 +828,7 @@ macro_rules! spi_dma { impl SpiRxDma<$SPIi, $RCi, PULL> { pub fn release(self) -> (Spi<$SPIi, u8, PULL>, $RCi) { let SpiRxDma { payload, channel } = self; - payload.spi.cr2.modify(|_, w| w.rxdmaen().clear_bit()); + payload.spi.cr2().modify(|_, w| w.rxdmaen().clear_bit()); (payload, channel) } } @@ -843,7 +842,7 @@ macro_rules! spi_dma { } = self; payload .spi - .cr2 + .cr2() .modify(|_, w| w.rxdmaen().clear_bit().txdmaen().clear_bit()); (payload, rxchannel, txchannel) } @@ -886,13 +885,15 @@ macro_rules! spi_dma { // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it // until the end of the transfer. let (ptr, len) = unsafe { buffer.write_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*<$SPIi>::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -920,13 +921,15 @@ macro_rules! spi_dma { // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it // until the end of the transfer. let (ptr, len) = unsafe { buffer.read_buffer() }; - self.channel - .set_peripheral_address(unsafe { (*<$SPIi>::ptr()).dr.as_ptr() as u32 }, false); + self.channel.set_peripheral_address( + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, + false, + ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -967,21 +970,21 @@ macro_rules! spi_dma { } self.rxchannel.set_peripheral_address( - unsafe { &(*<$SPIi>::ptr()).dr as *const _ as u32 }, + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, false, ); self.rxchannel.set_memory_address(rxptr as u32, true); self.rxchannel.set_transfer_length(rxlen); self.txchannel.set_peripheral_address( - unsafe { &(*<$SPIi>::ptr()).dr as *const _ as u32 }, + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, false, ); self.txchannel.set_memory_address(txptr as u32, true); self.txchannel.set_transfer_length(txlen); atomic::compiler_fence(Ordering::Release); - self.rxchannel.ch().cr.modify(|_, w| { + self.rxchannel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -995,7 +998,7 @@ macro_rules! spi_dma { // write to memory w.dir().clear_bit() }); - self.txchannel.ch().cr.modify(|_, w| { + self.txchannel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -1044,14 +1047,14 @@ macro_rules! spi_dma { impl SpiSlave<$SPIi, u8, Otype, PULL> { pub fn with_tx_dma(self, channel: $TCi) -> SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL> { - self.spi.cr2.modify(|_, w| w.txdmaen().set_bit()); + self.spi.cr2().modify(|_, w| w.txdmaen().set_bit()); SpiSlaveTxDma { payload: self, channel, } } pub fn with_rx_dma(self, channel: $RCi) -> SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL> { - self.spi.cr2.modify(|_, w| w.rxdmaen().set_bit()); + self.spi.cr2().modify(|_, w| w.rxdmaen().set_bit()); SpiSlaveRxDma { payload: self, channel, @@ -1063,7 +1066,7 @@ macro_rules! spi_dma { txchannel: $TCi, ) -> SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL> { self.spi - .cr2 + .cr2() .modify(|_, w| w.rxdmaen().set_bit().txdmaen().set_bit()); SpiSlaveRxTxDma { payload: self, @@ -1076,7 +1079,7 @@ macro_rules! spi_dma { impl SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL> { pub fn release(self) -> (SpiSlave<$SPIi, u8, Otype, PULL>, $TCi) { let SpiSlaveTxDma { payload, channel } = self; - payload.spi.cr2.modify(|_, w| w.txdmaen().clear_bit()); + payload.spi.cr2().modify(|_, w| w.txdmaen().clear_bit()); (payload, channel) } } @@ -1084,7 +1087,7 @@ macro_rules! spi_dma { impl SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL> { pub fn release(self) -> (SpiSlave<$SPIi, u8, Otype, PULL>, $RCi) { let SpiSlaveRxDma { payload, channel } = self; - payload.spi.cr2.modify(|_, w| w.rxdmaen().clear_bit()); + payload.spi.cr2().modify(|_, w| w.rxdmaen().clear_bit()); (payload, channel) } } @@ -1098,7 +1101,7 @@ macro_rules! spi_dma { } = self; payload .spi - .cr2 + .cr2() .modify(|_, w| w.rxdmaen().clear_bit().txdmaen().clear_bit()); (payload, rxchannel, txchannel) } @@ -1142,14 +1145,14 @@ macro_rules! spi_dma { // until the end of the transfer. let (ptr, len) = unsafe { buffer.write_buffer() }; self.channel.set_peripheral_address( - unsafe { &(*<$SPIi>::ptr()).dr as *const _ as u32 }, + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, false, ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -1178,14 +1181,14 @@ macro_rules! spi_dma { // until the end of the transfer. let (ptr, len) = unsafe { buffer.read_buffer() }; self.channel.set_peripheral_address( - unsafe { &(*<$SPIi>::ptr()).dr as *const _ as u32 }, + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, false, ); self.channel.set_memory_address(ptr as u32, true); self.channel.set_transfer_length(len); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { + self.channel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -1225,18 +1228,22 @@ macro_rules! spi_dma { panic!("receive and send buffer lengths do not match!"); } - self.rxchannel - .set_peripheral_address(unsafe { (*<$SPIi>::ptr()).dr.as_ptr() as u32 }, false); + self.rxchannel.set_peripheral_address( + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, + false, + ); self.rxchannel.set_memory_address(rxptr as u32, true); self.rxchannel.set_transfer_length(rxlen); - self.txchannel - .set_peripheral_address(unsafe { (*<$SPIi>::ptr()).dr.as_ptr() as u32 }, false); + self.txchannel.set_peripheral_address( + unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 }, + false, + ); self.txchannel.set_memory_address(txptr as u32, true); self.txchannel.set_transfer_length(txlen); atomic::compiler_fence(Ordering::Release); - self.rxchannel.ch().cr.modify(|_, w| { + self.rxchannel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level @@ -1250,7 +1257,7 @@ macro_rules! spi_dma { // write to memory w.dir().clear_bit() }); - self.txchannel.ch().cr.modify(|_, w| { + self.txchannel.ch().cr().modify(|_, w| { // memory to memory mode disabled w.mem2mem().clear_bit(); // medium channel priority level diff --git a/src/timer.rs b/src/timer.rs index e3a245df..ead731f4 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -325,7 +325,7 @@ macro_rules! hal { } #[inline(always)] unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) { - self.arr.write(|w| w.bits(arr)) + self.arr().write(|w| w.bits(arr)) } #[inline(always)] fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> { @@ -340,83 +340,85 @@ macro_rules! hal { #[inline(always)] fn read_auto_reload() -> u32 { let tim = unsafe { &*<$TIM>::ptr() }; - tim.arr.read().bits() + tim.arr().read().bits() } #[inline(always)] fn enable_preload(&mut self, b: bool) { - self.cr1.modify(|_, w| w.arpe().bit(b)); + self.cr1().modify(|_, w| w.arpe().bit(b)); } #[inline(always)] fn enable_counter(&mut self) { - self.cr1.modify(|_, w| w.cen().set_bit()); + self.cr1().modify(|_, w| w.cen().set_bit()); } #[inline(always)] fn disable_counter(&mut self) { - self.cr1.modify(|_, w| w.cen().clear_bit()); + self.cr1().modify(|_, w| w.cen().clear_bit()); } #[inline(always)] fn is_counter_enabled(&self) -> bool { - self.cr1.read().cen().is_enabled() + self.cr1().read().cen().is_enabled() } #[inline(always)] fn reset_counter(&mut self) { - self.cnt.reset(); + self.cnt().reset(); } #[inline(always)] fn set_prescaler(&mut self, psc: u16) { - self.psc.write(|w| w.psc().bits(psc) ); + self.psc().write(|w| w.psc().set(psc) ); } #[inline(always)] fn read_prescaler(&self) -> u16 { - self.psc.read().psc().bits() + self.psc().read().psc().bits() } #[inline(always)] fn trigger_update(&mut self) { // Sets the URS bit to prevent an interrupt from being triggered by // the UG bit - self.cr1.modify(|_, w| w.urs().set_bit()); - self.egr.write(|w| w.ug().set_bit()); - self.cr1.modify(|_, w| w.urs().clear_bit()); + self.cr1().modify(|_, w| w.urs().set_bit()); + self.egr().write(|w| w.ug().set_bit()); + self.cr1().modify(|_, w| w.urs().clear_bit()); } #[inline(always)] fn clear_interrupt_flag(&mut self, event: Event) { - self.sr.write(|w| unsafe { w.bits(0xffff & !event.bits()) }); + self.sr().write(|w| unsafe { w.bits(0xffff & !event.bits()) }); } #[inline(always)] fn listen_interrupt(&mut self, event: Event, b: bool) { - if b { - self.dier.modify(|r, w| unsafe { w.bits(r.bits() | event.bits()) }); - } else { - self.dier.modify(|r, w| unsafe { w.bits(r.bits() & !event.bits()) }); - } + self.dier().modify(|r, w| unsafe { w.bits( + if b { + r.bits() | event.bits() + } else { + r.bits() & !event.bits() + } + ) }); } #[inline(always)] fn get_interrupt_flag(&self) -> Event { - Event::from_bits_truncate(self.sr.read().bits()) + Event::from_bits_truncate(self.sr().read().bits()) } #[inline(always)] fn read_count(&self) -> Self::Width { - self.cnt.read().bits() as Self::Width + self.cnt().read().bits() as Self::Width } #[inline(always)] fn start_one_pulse(&mut self) { - self.cr1.modify(|_, w| w.opm().set_bit().cen().set_bit()); + self.cr1().modify(|_, w| w.opm().set_bit().cen().set_bit()); } #[inline(always)] fn cr1_reset(&mut self) { - self.cr1.reset(); + self.cr1().reset(); } #[inline(always)] fn stop_in_debug(&mut self, dbg: &mut DBG, state: bool) { - dbg.cr.modify(|_, w| w.$dbg_timX_stop().bit(state)); + dbg.cr().modify(|_, w| w.$dbg_timX_stop().bit(state)); } } $(with_pwm!($TIM: $cnum $(, $aoe)?);)? $(impl MasterTimer for $TIM { - type Mms = pac::$timbase::cr2::MMS_A; + type Mms = pac::$timbase::cr2::MMS; fn master_mode(&mut self, mode: Self::Mms) { - self.cr2.modify(|_,w| w.mms().variant(mode)); + self.cr2().modify(|_,w| w.mms().variant(mode)); } })? )+ @@ -432,7 +434,7 @@ macro_rules! with_pwm { fn read_cc_value(channel: u8) -> u32 { let tim = unsafe { &*<$TIM>::ptr() }; if channel < Self::CH_NUMBER { - tim.ccr[channel as usize].read().bits() + tim.ccr(channel as usize).read().bits() } else { 0 } @@ -443,7 +445,7 @@ macro_rules! with_pwm { let tim = unsafe { &*<$TIM>::ptr() }; #[allow(unused_unsafe)] if channel < Self::CH_NUMBER { - tim.ccr[channel as usize].write(|w| unsafe { w.bits(value) }) + tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }) } } @@ -452,7 +454,7 @@ macro_rules! with_pwm { match channel { Channel::C1 => { self.ccmr1_output() - .modify(|_, w| w.oc1pe().set_bit().oc1m().bits(mode as _) ); + .modify(|_, w| w.oc1pe().set_bit().oc1m().set(mode as _) ); } _ => {}, } @@ -460,14 +462,14 @@ macro_rules! with_pwm { #[inline(always)] fn start_pwm(&mut self) { - self.cr1.modify(|_, w| w.cen().set_bit()); + self.cr1().modify(|_, w| w.cen().set_bit()); } #[inline(always)] fn enable_channel(c: u8, b: bool) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4, b); } + unsafe { bb::write(tim.ccer(), c*4, b); } } } } @@ -480,7 +482,7 @@ macro_rules! with_pwm { fn read_cc_value(channel: u8) -> u32 { let tim = unsafe { &*<$TIM>::ptr() }; if channel < Self::CH_NUMBER { - tim.ccr[channel as usize].read().bits() + tim.ccr(channel as usize).read().bits() } else { 0 } @@ -491,7 +493,7 @@ macro_rules! with_pwm { let tim = unsafe { &*<$TIM>::ptr() }; #[allow(unused_unsafe)] if channel < Self::CH_NUMBER { - tim.ccr[channel as usize].write(|w| unsafe { w.bits(value) }) + tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }) } } @@ -500,11 +502,11 @@ macro_rules! with_pwm { match channel { Channel::C1 => { self.ccmr1_output() - .modify(|_, w| w.oc1pe().set_bit().oc1m().bits(mode as _) ); + .modify(|_, w| w.oc1pe().set_bit().oc1m().set(mode as _) ); } Channel::C2 => { self.ccmr1_output() - .modify(|_, w| w.oc2pe().set_bit().oc2m().bits(mode as _) ); + .modify(|_, w| w.oc2pe().set_bit().oc2m().set(mode as _) ); } _ => {}, } @@ -512,14 +514,14 @@ macro_rules! with_pwm { #[inline(always)] fn start_pwm(&mut self) { - self.cr1.modify(|_, w| w.cen().set_bit()); + self.cr1().modify(|_, w| w.cen().set_bit()); } #[inline(always)] fn enable_channel(c: u8, b: bool) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4, b); } + unsafe { bb::write(tim.ccer(), c*4, b); } } } } @@ -531,13 +533,13 @@ macro_rules! with_pwm { #[inline(always)] fn read_cc_value(channel: u8) -> u32 { let tim = unsafe { &*<$TIM>::ptr() }; - tim.ccr[channel as usize].read().bits() + tim.ccr(channel as usize).read().bits() } #[inline(always)] fn set_cc_value(channel: u8, value: u32) { let tim = unsafe { &*<$TIM>::ptr() }; - tim.ccr[channel as usize].write(|w| unsafe { w.bits(value) }) + tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }) } #[inline(always)] @@ -545,34 +547,34 @@ macro_rules! with_pwm { match channel { Channel::C1 => { self.ccmr1_output() - .modify(|_, w| w.oc1pe().set_bit().oc1m().bits(mode as _) ); + .modify(|_, w| w.oc1pe().set_bit().oc1m().set(mode as _) ); } Channel::C2 => { self.ccmr1_output() - .modify(|_, w| w.oc2pe().set_bit().oc2m().bits(mode as _) ); + .modify(|_, w| w.oc2pe().set_bit().oc2m().set(mode as _) ); } Channel::C3 => { self.ccmr2_output() - .modify(|_, w| w.oc3pe().set_bit().oc3m().bits(mode as _) ); + .modify(|_, w| w.oc3pe().set_bit().oc3m().set(mode as _) ); } Channel::C4 => { self.ccmr2_output() - .modify(|_, w| w.oc4pe().set_bit().oc4m().bits(mode as _) ); + .modify(|_, w| w.oc4pe().set_bit().oc4m().set(mode as _) ); } } } #[inline(always)] fn start_pwm(&mut self) { - $(let $aoe = self.bdtr.modify(|_, w| w.aoe().set_bit());)? - self.cr1.modify(|_, w| w.cen().set_bit()); + $(let $aoe = self.bdtr().modify(|_, w| w.aoe().set_bit());)? + self.cr1().modify(|_, w| w.cen().set_bit()); } #[inline(always)] fn enable_channel(c: u8, b: bool) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - unsafe { bb::write(&tim.ccer, c*4, b); } + unsafe { bb::write(tim.ccer(), c*4, b); } } } } diff --git a/src/timer/monotonic.rs b/src/timer/monotonic.rs index 28ff7949..80c96134 100644 --- a/src/timer/monotonic.rs +++ b/src/timer/monotonic.rs @@ -60,12 +60,12 @@ macro_rules! mono { impl MonoTimer<$TIM, FREQ> { fn _new(timer: FTimer<$TIM, FREQ>) -> Self { - timer.tim.arr.write(|w| w.arr().bits(u16::MAX)); // Set auto-reload value. - timer.tim.egr.write(|w| w.ug().set_bit()); // Generate interrupt on overflow. + timer.tim.arr().write(|w| w.arr().set(u16::MAX)); // Set auto-reload value. + timer.tim.egr().write(|w| w.ug().set_bit()); // Generate interrupt on overflow. // Start timer. - timer.tim.sr.modify(|_, w| w.uif().clear_bit()); // Clear interrupt flag. - timer.tim.cr1.modify(|_, w| { + timer.tim.sr().modify(|_, w| w.uif().clear_bit()); // Clear interrupt flag. + timer.tim.cr1().modify(|_, w| { w.cen() .set_bit() // Enable counter. .udis() @@ -83,16 +83,16 @@ macro_rules! mono { type Duration = fugit::TimerDurationU32; unsafe fn reset(&mut self) { - self.tim.dier.modify(|_, w| w.cc1ie().set_bit()); + self.tim.dier().modify(|_, w| w.cc1ie().set_bit()); } #[inline(always)] fn now(&mut self) -> Self::Instant { - let cnt = self.tim.cnt.read().cnt().bits() as u32; + let cnt = self.tim.cnt().read().cnt().bits() as u32; // If the overflow bit is set, we add this to the timer value. It means the `on_interrupt` // has not yet happened, and we need to compensate here. - let ovf = if self.tim.sr.read().uif().bit_is_set() { + let ovf = if self.tim.sr().read().uif().bit_is_set() { 0x10000 } else { 0 @@ -103,7 +103,7 @@ macro_rules! mono { fn set_compare(&mut self, instant: Self::Instant) { let now = self.now(); - let cnt = self.tim.cnt.read().cnt().bits(); + let cnt = self.tim.cnt().read().cnt().bits(); // Since the timer may or may not overflow based on the requested compare val, we check // how many ticks are left. @@ -113,17 +113,17 @@ macro_rules! mono { Some(_) => cnt.wrapping_add(0xffff), // Will overflow, run for as long as possible }; - self.tim.ccr1().write(|w| w.ccr().bits(val)); + self.tim.ccr1().write(|w| w.ccr().set(val)); } fn clear_compare_flag(&mut self) { - self.tim.sr.modify(|_, w| w.cc1if().clear_bit()); + self.tim.sr().modify(|_, w| w.cc1if().clear_bit()); } fn on_interrupt(&mut self) { // If there was an overflow, increment the overflow counter. - if self.tim.sr.read().uif().bit_is_set() { - self.tim.sr.modify(|_, w| w.uif().clear_bit()); + if self.tim.sr().read().uif().bit_is_set() { + self.tim.sr().modify(|_, w| w.uif().clear_bit()); self.ovf += 0x10000; } diff --git a/src/timer/pwm_input.rs b/src/timer/pwm_input.rs index d20e4701..b7f00ab0 100644 --- a/src/timer/pwm_input.rs +++ b/src/timer/pwm_input.rs @@ -182,14 +182,14 @@ macro_rules! hal { use Configuration::*; // Disable capture on both channels during setting // (for Channel X bit is CCXE) - tim.ccer.modify(|_,w| w.cc1e().clear_bit().cc2e().clear_bit() + tim.ccer().modify(|_,w| w.cc1e().clear_bit().cc2e().clear_bit() .cc1p().clear_bit().cc2p().set_bit()); // Define the direction of the channel (input/output) // and the used input tim.ccmr1_input().modify( |_,w| w.cc1s().ti1().cc2s().ti1()); - tim.dier.write(|w| w.cc1ie().set_bit()); + tim.dier().write(|w| w.cc1ie().set_bit()); // Configure slave mode control register // Selects the trigger input to be used to synchronize the counter @@ -198,39 +198,39 @@ macro_rules! hal { // Slave Mode Selection : // 100: Reset Mode - Rising edge of the selected trigger input (TRGI) // reinitializes the counter and generates an update of the registers. - tim.smcr.modify( |_,w| unsafe {w.ts().bits(0b101).sms().bits(0b100)}); + tim.smcr().modify( |_,w| unsafe {w.ts().bits(0b101).sms().bits(0b100)}); match mode { Frequency(f) => { let freq = f.raw(); let max_freq = if freq > 5 {freq/5} else {1}; let (arr,presc) = compute_arr_presc(max_freq, clk.raw()); - tim.arr.write(|w| w.arr().bits(arr)); - tim.psc.write(|w| w.psc().bits(presc) ); + tim.arr().write(|w| w.arr().set(arr)); + tim.psc().write(|w| w.psc().set(presc) ); }, DutyCycle(f) => { let freq = f.raw(); let max_freq = if freq > 2 {freq/2 + freq/4 + freq/8} else {1}; let (arr,presc) = compute_arr_presc(max_freq, clk.raw()); - tim.arr.write(|w| w.arr().bits(arr)); - tim.psc.write(|w| w.psc().bits(presc) ); + tim.arr().write(|w| w.arr().set(arr)); + tim.psc().write(|w| w.psc().set(presc) ); }, RawFrequency(f) => { let freq = f.raw(); let (arr,presc) = compute_arr_presc(freq, clk.raw()); - tim.arr.write(|w| w.arr().bits(arr)); - tim.psc.write(|w| w.psc().bits(presc) ); + tim.arr().write(|w| w.arr().set(arr)); + tim.psc().write(|w| w.psc().set(presc) ); } RawValues{arr, presc} => { - tim.arr.write(|w| w.arr().bits(arr)); - tim.psc.write(|w| w.psc().bits(presc) ); + tim.arr().write(|w| w.arr().set(arr)); + tim.psc().write(|w| w.psc().set(presc) ); } } // Enable Capture on both channels - tim.ccer.modify(|_,w| w.cc1e().set_bit().cc2e().set_bit()); + tim.ccer().modify(|_,w| w.cc1e().set_bit().cc2e().set_bit()); - tim.cr1.modify(|_,w| w.cen().set_bit()); + tim.cr1().modify(|_,w| w.cen().set_bit()); unsafe { mem::MaybeUninit::uninit().assume_init() } } @@ -245,7 +245,7 @@ macro_rules! hal { self.wait_for_capture(); } - let presc = unsafe { (*$TIMX::ptr()).psc.read().bits() as u16}; + let presc = unsafe { (*$TIMX::ptr()).psc().read().bits() as u16}; let ccr1 = unsafe { (*$TIMX::ptr()).ccr1().read().bits() as u16}; // Formulas : @@ -289,8 +289,8 @@ macro_rules! hal { /// Wait until the timer has captured a period fn wait_for_capture(&self) { - unsafe { (*$TIMX::ptr()).sr.write(|w| w.uif().clear_bit().cc1if().clear_bit().cc1of().clear_bit())}; - while unsafe { (*$TIMX::ptr()).sr.read().cc1if().bit_is_clear()} {} + unsafe { (*$TIMX::ptr()).sr().write(|w| w.uif().clear_bit().cc1if().clear_bit().cc1of().clear_bit())}; + while unsafe { (*$TIMX::ptr()).sr().read().cc1if().bit_is_clear()} {} } } )+ diff --git a/src/watchdog.rs b/src/watchdog.rs index 8009585c..c939b70a 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -27,7 +27,7 @@ impl IndependentWatchdog { /// Debug independent watchdog stopped when core is halted pub fn stop_on_debug(&self, dbg: &DBG, stop: bool) { - dbg.cr.modify(|_, w| w.dbg_iwdg_stop().bit(stop)); + dbg.cr().modify(|_, w| w.dbg_iwdg_stop().bit(stop)); } fn setup(&self, timeout_ms: u32) { @@ -41,21 +41,21 @@ impl IndependentWatchdog { let rl = (timeout_ms * max_rl / max_period).min(max_rl) as u16; self.access_registers(|iwdg| { - iwdg.pr.modify(|_, w| w.pr().bits(pr)); - iwdg.rlr.modify(|_, w| w.rl().bits(rl)); + iwdg.pr().modify(|_, w| unsafe { w.pr().bits(pr) }); + iwdg.rlr().modify(|_, w| w.rl().set(rl)); }); } fn is_pr_updating(&self) -> bool { - self.iwdg.sr.read().pvu().bit() + self.iwdg.sr().read().pvu().bit() } /// Returns the interval in ms pub fn interval(&self) -> MilliSeconds { while self.is_pr_updating() {} - let pr = self.iwdg.pr.read().pr().bits(); - let rl = self.iwdg.rlr.read().rl().bits(); + let pr = self.iwdg.pr().read().pr().bits(); + let rl = self.iwdg.rlr().read().rl().bits(); let ms = Self::timeout_period(pr, rl); ms.millis() } @@ -80,22 +80,22 @@ impl IndependentWatchdog { fn access_registers A>(&self, mut f: F) -> A { // Unprotect write access to registers - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_ACCESS) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_ACCESS) }); let a = f(&self.iwdg); // Protect again - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_RELOAD) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_RELOAD) }); a } pub fn start(&mut self, period: MilliSeconds) { self.setup(period.ticks()); - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_START) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_START) }); } pub fn feed(&mut self) { - self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_RELOAD) }); + self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_RELOAD) }); } }