diff --git a/CHANGELOG.md b/CHANGELOG.md index 399b2eb3..e57e72a7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -23,6 +23,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Fix CAN2 remap - `Adc::new` instead of `Adc::adcX` and `AdcExt` trait - Update `bxcan`, `heapless`, `mfrc522`, reenable `mpu9250` example [#513] - PWM timer auto reload value is now preloaded/buffered [#453] diff --git a/examples/can-echo.rs b/examples/can-echo.rs index 725c3670..b35c8c39 100644 --- a/examples/can-echo.rs +++ b/examples/can-echo.rs @@ -46,8 +46,12 @@ fn main() -> ! { #[cfg(feature = "connectivity")] let _can2 = { + let mut afio = dp.AFIO.constrain(&mut rcc); let gpiob = dp.GPIOB.split(&mut rcc); - let can = dp.CAN2.can((gpiob.pb6, gpiob.pb5), &mut rcc); + let can = dp + .CAN2 + .remap(&mut afio.mapr) + .can((gpiob.pb6, gpiob.pb5), &mut rcc); // APB1 (PCLK1): 8MHz, Bit rate: 125kBit/s, Sample Point 87.5% // Value was calculated with http://www.bittiming.can-wiki.info/ diff --git a/examples/serial-dma-circ.rs b/examples/serial-dma-circ.rs index 05ccaddc..f4776a9d 100644 --- a/examples/serial-dma-circ.rs +++ b/examples/serial-dma-circ.rs @@ -23,7 +23,7 @@ fn main() -> ! { let mut rcc = p.RCC.constrain(); - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); let channels = p.DMA1.split(&mut rcc); let mut gpioa = p.GPIOA.split(&mut rcc); diff --git a/examples/serial-dma-peek.rs b/examples/serial-dma-peek.rs index 8f3b025b..48d8c6a2 100644 --- a/examples/serial-dma-peek.rs +++ b/examples/serial-dma-peek.rs @@ -22,7 +22,7 @@ fn main() -> ! { let mut rcc = p.RCC.constrain(); - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); let channels = p.DMA1.split(&mut rcc); let mut gpioa = p.GPIOA.split(&mut rcc); diff --git a/examples/serial-fmt.rs b/examples/serial-fmt.rs index ad3ae9b7..08b1c545 100644 --- a/examples/serial-fmt.rs +++ b/examples/serial-fmt.rs @@ -27,7 +27,7 @@ fn main() -> ! { let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); // Prepare the GPIOB peripheral let mut gpiob = p.GPIOB.split(&mut rcc); diff --git a/examples/serial_9bits.rs b/examples/serial_9bits.rs index baffa555..b4054ed8 100644 --- a/examples/serial_9bits.rs +++ b/examples/serial_9bits.rs @@ -102,7 +102,7 @@ fn main() -> ! { let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers. - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); // Prepare the GPIOB peripheral. let gpiob = p.GPIOB.split(&mut rcc); diff --git a/examples/serial_config.rs b/examples/serial_config.rs index 4c623757..70134ca2 100644 --- a/examples/serial_config.rs +++ b/examples/serial_config.rs @@ -24,7 +24,7 @@ fn main() -> ! { let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); // Prepare the GPIOB peripheral let mut gpiob = p.GPIOB.split(&mut rcc); diff --git a/examples/serial_reconfigure.rs b/examples/serial_reconfigure.rs index 7a0d9cf8..ddd0aefa 100644 --- a/examples/serial_reconfigure.rs +++ b/examples/serial_reconfigure.rs @@ -28,7 +28,7 @@ fn main() -> ! { let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); // Prepare the GPIOB peripheral let mut gpiob = p.GPIOB.split(&mut rcc); diff --git a/examples/spi.rs b/examples/spi.rs index 1d04238f..d599170f 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -23,7 +23,7 @@ fn setup() -> (Spi, PA4) { let mut rcc = dp.RCC.constrain(); - //let mut afio = dp.AFIO.constrain(); + //let mut afio = dp.AFIO.constrain(&mut rcc); let mut gpioa = dp.GPIOA.split(&mut rcc); // SPI1 diff --git a/src/afio.rs b/src/afio.rs index 8ec619e1..b7852792 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -35,7 +35,7 @@ impl AfioExt for AFIO { /// ```rust /// let p = pac::Peripherals::take().unwrap(); /// let mut rcc = p.RCC.constrain(); -/// let mut afio = p.AFIO.constrain(); +/// let mut afio = p.AFIO.constrain(&mut rcc); pub struct Parts { pub evcr: EVCR, pub mapr: MAPR, @@ -62,7 +62,7 @@ impl EVCR { /// ```rust /// let dp = pac::Peripherals::take().unwrap(); /// let mut rcc = dp.RCC.constrain(); -/// let mut afio = dp.AFIO.constrain(); +/// let mut afio = dp.AFIO.constrain(&mut rcc); /// function_using_mapr(&mut afio.mapr); /// ``` #[non_exhaustive] @@ -318,14 +318,14 @@ pub mod can2 { pin! { > for [ - PB6: [0], - PB13: [1], + PB13: [0], + PB6: [1], ], } pin! { default:Floating for [ - PB5: [0], - PB12: [1], + PB12: [0], + PB5: [1], ], } diff --git a/src/lib.rs b/src/lib.rs index c062a6ab..bc3b362c 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -62,7 +62,7 @@ //! let clocks = rcc.cfgr.freeze(&mut flash.acr); //! //! // Prepare the alternate function I/O registers -//! let mut afio = dp.AFIO.constrain(); +//! let mut afio = dp.AFIO.constrain(&mut rcc); //! ``` //! //! ## Usage examples diff --git a/src/serial.rs b/src/serial.rs index a8d2e2e5..99a665ee 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -55,8 +55,8 @@ //! let mut flash = dp.FLASH.constrain(); //! let mut rcc = dp.RCC.constrain(); //! let clocks = rcc.cfgr.freeze(&mut flash.acr); -//! let mut afio = dp.AFIO.constrain(); -//! let mut gpioa = dp.GPIOA.split(); +//! let mut afio = dp.AFIO.constrain(&mut rcc); +//! let mut gpioa = dp.GPIOA.split(&mut rcc); //! //! // USART1 on Pins A9 and A10 //! let pin_tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);