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1 |
| -//Based on stm32hal by David-OConnor |
| 1 | +//! Digital-to-Analog Converter |
| 2 | +
|
| 3 | +// Based on stm32hal by David-OConnor |
2 | 4 |
|
3 | 5 | use cortex_m::asm;
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4 | 6 |
|
5 | 7 | use crate::{
|
6 | 8 | gpio::{self, Analog},
|
7 | 9 | pac::{dac1, DAC1},
|
8 |
| - rcc::{Rcc, Clocks, AHB, APB1}, |
| 10 | + rcc::{Clocks, Enable, Rcc, Reset, AHB, APB1}, |
9 | 11 | };
|
10 | 12 |
|
11 |
| -#[cfg(any( |
12 |
| - feature = "stm32f303xb", |
13 |
| - feature = "stm32f303xc", |
14 |
| - feature = "stm32f303xd", |
15 |
| - feature = "stm32f303xe", |
16 |
| -))] |
17 |
| -use crate::pac::DMA1::{self}; |
| 13 | +use crate::pac::DMA1; |
18 | 14 |
|
19 | 15 | use crate::pac::{self, rcc, RCC};
|
20 | 16 |
|
21 |
| -pub enum DacChannel { |
22 |
| - One, |
23 |
| - Two, |
24 |
| -} |
25 |
| - |
26 | 17 | /// Represents a Digital to Analog Converter (DAC) peripheral.
|
27 | 18 | pub struct Dac {
|
28 | 19 | regs: DAC1,
|
29 | 20 | }
|
30 | 21 |
|
31 |
| -// todo: Calculate the VDDA vref, as you do with onboard ADCs! |
32 | 22 | impl Dac {
|
33 |
| - /// Initialize a DAC peripheral, including enabling and resetting |
| 23 | + /// Initializes the DAC peripheral. |
| 24 | + pub fn new(regs: DAC1, apb1: &mut APB1) -> Self { |
| 25 | + DAC1::enable(apb1); |
| 26 | + DAC1::reset(apb1); |
34 | 27 |
|
35 |
| - pub fn new(regs: DAC1, abp1: &mut APB1) -> Self { |
36 |
| - |
37 |
| - abp1.enr().modify(|_, w| w.dac1en().set_bit()); |
38 |
| - abp1.rstr().modify(|_, w| w.dac1rst().set_bit()); |
39 |
| - abp1.rstr().modify(|_, w| w.dac1rst().clear_bit()); |
| 28 | + // Enable channel 1. |
| 29 | + regs.cr.modify(|_, w| w.en1().set_bit()); |
40 | 30 |
|
41 | 31 | Self { regs }
|
42 | 32 | }
|
43 | 33 |
|
44 |
| - pub fn enable_channel(&mut self, channel: DacChannel) { |
45 |
| - let cr = &self.regs.cr; |
46 |
| - |
47 |
| - cr.modify(|_, w| match channel { |
48 |
| - DacChannel::One => w.en1().set_bit(), |
49 |
| - DacChannel::Two => w.en2().set_bit(), |
50 |
| - }); |
51 |
| - } |
52 |
| - |
53 |
| - /// the data parameter MUST be a 12-bit value -- values outside that range will result in misbehavior |
| 34 | + /// Writes a sample to the Channel 1 output register. |
| 35 | + /// |
| 36 | + /// Only the low 12 bits of `data` will be used, the rest is ignored. |
54 | 37 | pub fn write_data(&mut self, data: u16) {
|
55 |
| - |
56 | 38 | self.regs.dhr12r1.write(|w| w.dacc1dhr().bits(data))
|
57 | 39 | }
|
58 | 40 | }
|
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