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test: Increase uart test clock speed
This is to potentially better catch erros like described in #260 ealier.
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testsuite/tests/uart.rs

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,11 @@ mod tests {
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let mut rcc = dp.RCC.constrain();
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let mut flash = dp.FLASH.constrain();
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let clocks = rcc.cfgr.freeze(&mut flash.acr);
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let clocks = rcc
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.cfgr
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.use_hse(8.MHz())
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.sysclk(64.MHz())
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.freeze(&mut flash.acr);
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let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
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let mut gpiob = dp.GPIOB.split(&mut rcc.ahb);
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