@@ -595,53 +595,50 @@ impl CFGR {
595
595
pub fn freeze ( self , acr : & mut ACR ) -> Clocks {
596
596
let ( sysclk, sysclk_source, pll_config) = self . get_sysclk ( ) ;
597
597
598
- let ( hpre_bits, hpre) = self
599
- . hclk
600
- . map ( |hclk| match sysclk / hclk {
601
- 0 => unreachable ! ( ) ,
602
- 1 => ( cfgr:: HPRE_A :: DIV1 , 1 ) ,
603
- 2 => ( cfgr:: HPRE_A :: DIV2 , 2 ) ,
604
- 3 ..=5 => ( cfgr:: HPRE_A :: DIV4 , 4 ) ,
605
- 6 ..=11 => ( cfgr:: HPRE_A :: DIV8 , 8 ) ,
606
- 12 ..=39 => ( cfgr:: HPRE_A :: DIV16 , 16 ) ,
607
- 40 ..=95 => ( cfgr:: HPRE_A :: DIV64 , 64 ) ,
608
- 96 ..=191 => ( cfgr:: HPRE_A :: DIV128 , 128 ) ,
609
- 192 ..=383 => ( cfgr:: HPRE_A :: DIV256 , 256 ) ,
610
- _ => ( cfgr:: HPRE_A :: DIV512 , 512 ) ,
611
- } )
612
- . unwrap_or ( ( cfgr:: HPRE_A :: DIV1 , 1 ) ) ;
598
+ let ( hpre_bits, hpre) =
599
+ self . hclk
600
+ . map_or ( ( cfgr:: HPRE_A :: DIV1 , 1 ) , |hclk| match sysclk / hclk {
601
+ 0 => unreachable ! ( ) ,
602
+ 1 => ( cfgr:: HPRE_A :: DIV1 , 1 ) ,
603
+ 2 => ( cfgr:: HPRE_A :: DIV2 , 2 ) ,
604
+ 3 ..=5 => ( cfgr:: HPRE_A :: DIV4 , 4 ) ,
605
+ 6 ..=11 => ( cfgr:: HPRE_A :: DIV8 , 8 ) ,
606
+ 12 ..=39 => ( cfgr:: HPRE_A :: DIV16 , 16 ) ,
607
+ 40 ..=95 => ( cfgr:: HPRE_A :: DIV64 , 64 ) ,
608
+ 96 ..=191 => ( cfgr:: HPRE_A :: DIV128 , 128 ) ,
609
+ 192 ..=383 => ( cfgr:: HPRE_A :: DIV256 , 256 ) ,
610
+ _ => ( cfgr:: HPRE_A :: DIV512 , 512 ) ,
611
+ } ) ;
613
612
614
613
let hclk: u32 = sysclk / hpre;
615
614
616
615
assert ! ( hclk <= 72_000_000 ) ;
617
616
618
- let ( ppre1_bits, ppre1) = self
619
- . pclk1
620
- . map ( |pclk1| match hclk / pclk1 {
621
- 0 => unreachable ! ( ) ,
622
- 1 => ( cfgr:: PPRE1_A :: DIV1 , 1 ) ,
623
- 2 => ( cfgr:: PPRE1_A :: DIV2 , 2 ) ,
624
- 3 ..=5 => ( cfgr:: PPRE1_A :: DIV4 , 4 ) ,
625
- 6 ..=11 => ( cfgr:: PPRE1_A :: DIV8 , 8 ) ,
626
- _ => ( cfgr:: PPRE1_A :: DIV16 , 16 ) ,
627
- } )
628
- . unwrap_or ( ( cfgr:: PPRE1_A :: DIV1 , 1 ) ) ;
617
+ let ( ppre1_bits, ppre1) =
618
+ self . pclk1
619
+ . map_or ( ( cfgr:: PPRE1_A :: DIV1 , 1 ) , |pclk1| match hclk / pclk1 {
620
+ 0 => unreachable ! ( ) ,
621
+ 1 => ( cfgr:: PPRE1_A :: DIV1 , 1 ) ,
622
+ 2 => ( cfgr:: PPRE1_A :: DIV2 , 2 ) ,
623
+ 3 ..=5 => ( cfgr:: PPRE1_A :: DIV4 , 4 ) ,
624
+ 6 ..=11 => ( cfgr:: PPRE1_A :: DIV8 , 8 ) ,
625
+ _ => ( cfgr:: PPRE1_A :: DIV16 , 16 ) ,
626
+ } ) ;
629
627
630
628
let pclk1 = hclk / u32:: from ( ppre1) ;
631
629
632
630
assert ! ( pclk1 <= 36_000_000 ) ;
633
631
634
- let ( ppre2_bits, ppre2) = self
635
- . pclk2
636
- . map ( |pclk2| match hclk / pclk2 {
637
- 0 => unreachable ! ( ) ,
638
- 1 => ( cfgr:: PPRE2_A :: DIV1 , 1 ) ,
639
- 2 => ( cfgr:: PPRE2_A :: DIV2 , 2 ) ,
640
- 3 ..=5 => ( cfgr:: PPRE2_A :: DIV4 , 4 ) ,
641
- 6 ..=11 => ( cfgr:: PPRE2_A :: DIV8 , 8 ) ,
642
- _ => ( cfgr:: PPRE2_A :: DIV16 , 16 ) ,
643
- } )
644
- . unwrap_or ( ( cfgr:: PPRE2_A :: DIV1 , 1 ) ) ;
632
+ let ( ppre2_bits, ppre2) =
633
+ self . pclk2
634
+ . map_or ( ( cfgr:: PPRE2_A :: DIV1 , 1 ) , |pclk2| match hclk / pclk2 {
635
+ 0 => unreachable ! ( ) ,
636
+ 1 => ( cfgr:: PPRE2_A :: DIV1 , 1 ) ,
637
+ 2 => ( cfgr:: PPRE2_A :: DIV2 , 2 ) ,
638
+ 3 ..=5 => ( cfgr:: PPRE2_A :: DIV4 , 4 ) ,
639
+ 6 ..=11 => ( cfgr:: PPRE2_A :: DIV8 , 8 ) ,
640
+ _ => ( cfgr:: PPRE2_A :: DIV16 , 16 ) ,
641
+ } ) ;
645
642
646
643
let pclk2 = hclk / u32:: from ( ppre2) ;
647
644
0 commit comments