Merge pull request #91 from jonathanpallant/fix_uart_overflow_sticky

Clear UART overflow bit.

Author: Sh3Rm4n

CHANGELOG.md

@@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Wrong default modes for debug GPIO pins
 - Wrong calculation of HCLK prescaler, if using a prescaler value equal or
   higher than 64 ([#42](https://github.com/stm32-rs/stm32f3xx-hal/pull/42))
+- UART reception error flags not cleared ([#91](https://github.com/stm32-rs/stm32f3xx-hal/pull/91))
 
 ## [v0.4.2] - 2020-03-21
 

src/serial.rs

@@ -319,13 +319,20 @@ macro_rules! hal {
                     // NOTE(unsafe) atomic read with no side effects
                     let isr = unsafe { (*$USARTX::ptr()).isr.read() };
 
+                    // NOTE(unsafe, write) write accessor for atomic writes with no side effects
+                    let icr = unsafe { &(*$USARTX::ptr()).icr };
+
                     Err(if isr.pe().bit_is_set() {
+                        icr.write(|w| w.pecf().clear());
                         nb::Error::Other(Error::Parity)
                     } else if isr.fe().bit_is_set() {
+                        icr.write(|w| w.fecf().clear());
                         nb::Error::Other(Error::Framing)
                     } else if isr.nf().bit_is_set() {
+                        icr.write(|w| w.ncf().clear());
                         nb::Error::Other(Error::Noise)
                     } else if isr.ore().bit_is_set() {
+                        icr.write(|w| w.orecf().clear());
                         nb::Error::Other(Error::Overrun)
                     } else if isr.rxne().bit_is_set() {
                         // NOTE(read_volatile) see `write_volatile` below