Merge pull request #189 from Piroro-hs/gpio-collapse

GPIO refactor (Simplify macro, reduce type states, and support interrupt)

Author: Sh3Rm4n

CHANGELOG.md

@@ -7,20 +7,34 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-## [v0.7.0] - 2021-03-10
-
 ### Added
 
-- Replace custom time based units with types defined in the [embedded-time][] crate ([#192])
 - Make `Clocks` `ppre1()` and `ppre2()` methods public, to get the current
   Prescaler value. ([#210])
+- Implement `into_xxx` methods for partially erased pins ([#189])
+- Enable better GPIO internal resistor configuration ([#189])
+- Support for GPIO output slew rate configuration ([#189])
+- Support for GPIO interrupts ([#189])
 
-### Breaking changes
+### Changed
 
+- Added support for more CAN bit rates and modes. ([#186])
+- The structure of `gpio.rs` is greatly changed. Generic `Pin` struct is used
+  for every GPIO pin now ([#189])
+
+### Fixed
+
+- Delay based on systick no longer panics ([#203]) for to high values
+  and support longer delays ([#208])
+
+### Breaking Changes
+
+- Replace custom time based units with types defined in the [embedded-time][]
+  crate ([#192])
 - The `rcc` public API now expects time based units in `Megahertz`.
   If the supplied frequency cannot be converted to `Hertz` the code
   will `panic`. This will occur if the supplied `Megahertz` frequency
-  cannot fit into `u32::MAX` when converting to `Hertz`
+  cannot fit into `u32::MAX` when converting to `Hertz` ([#192])
 
 ```rust
 // The supplied frequencies must be in `MHz`.
@@ -34,21 +48,17 @@ let clocks = rcc
 ```
 
 - Bump dependencies: ([#211])
-  - `stm32f3` dependency to 0.13.0
-  - `nb` to 1.0
+  - `stm32f3` dependency to 0.13
+  - `nb` to 1
   - `cortex-m` to 0.7
   - `stm32-usbd` to 0.6
   - `defmt` to 0.2
-
-[embedded-time]: https://github.com/FluenTech/embedded-time/
-### Changed
-
-- Added support for more CAN bit rates and modes. ([#186])
-
-### Fixed
-
-- Delay based on systick no longer panics ([#203]) for to high values
-  and support longer delays ([#208])
+- `into_afx` methods are splitted into `into_afx_push_pull` and
+  `into_afx_open_drain` ([#189])
+- GPIO output mode (`PushPull` or `OpenDrain`) is encoded into pin typestate
+  in alternate function mode ([#189])
+- GPIO internal resistor configuration is no longer encoded into pin typestate
+  in input mode ([#189])
 
 ## [v0.6.1] - 2020-12-10
 
@@ -69,8 +79,7 @@ let clocks = rcc
 - Impls for all SPI pins for all `stm32f302` sub-targets, `stm32f303`
   subtargets, `stm32f3x8` targets, `stm32f334`, and `stm32f373`
   ([#99])
-- SPI4 peripheral for supported
-  devices. ([#99])
+- SPI4 peripheral for supported devices. ([#99])
 - Support for I2C transfer of more than 255 bytes, and 0 byte write ([#154])
 - Support for HSE bypass and CSS ([#156])
 - Impls for missing I2C pin definitions ([#164])
@@ -85,9 +94,6 @@ let clocks = rcc
     The support of this feature is subject to change as the development
     of [defmt][] is advancing.
 
-[defmt]: https://github.com/knurling-rs/defmt
-[filter]: https://defmt.ferrous-systems.com/filtering.html
-
 ### Changed
 
 - Introduced auto-generated GPIO mappings based on the STM32CubeMX database
@@ -99,8 +105,6 @@ let clocks = rcc
   ([#152])
 - Wrong I2C clock source ([#164])
 
-[#151]: https://github.com/stm32-rs/stm32f3xx-hal/issues/151
-
 ### Breaking Changes
 
 - Removed impl for `SckPin<SPI2>` for `PB13<AF5>` from `stm32f328` and
@@ -305,20 +309,21 @@ let clocks = rcc
 
 - Support `stm32f303` device
 
+[embedded-time]: https://github.com/FluenTech/embedded-time/
+[defmt]: https://github.com/knurling-rs/defmt
+[filter]: https://defmt.ferrous-systems.com/filtering.html
+
 [#211]: https://github.com/stm32-rs/stm32f3xx-hal/pull/211
 [#210]: https://github.com/stm32-rs/stm32f3xx-hal/pull/210
 [#208]: https://github.com/stm32-rs/stm32f3xx-hal/pull/208
 [#203]: https://github.com/stm32-rs/stm32f3xx-hal/issues/203
 [#192]: https://github.com/stm32-rs/stm32f3xx-hal/pull/192
+[#189]: https://github.com/stm32-rs/stm32f3xx-hal/pull/189
 [#186]: https://github.com/stm32-rs/stm32f3xx-hal/pull/186
 [#184]: https://github.com/stm32-rs/stm32f3xx-hal/pull/184
 [#172]: https://github.com/stm32-rs/stm32f3xx-hal/pull/172
 [#170]: https://github.com/stm32-rs/stm32f3xx-hal/pull/170
 [#164]: https://github.com/stm32-rs/stm32f3xx-hal/pull/164
-[#164]: https://github.com/stm32-rs/stm32f3xx-hal/pull/164
-[#164]: https://github.com/stm32-rs/stm32f3xx-hal/pull/164
-[#164]: https://github.com/stm32-rs/stm32f3xx-hal/pull/164
-[#164]: https://github.com/stm32-rs/stm32f3xx-hal/pull/164
 [#156]: https://github.com/stm32-rs/stm32f3xx-hal/pull/156
 [#154]: https://github.com/stm32-rs/stm32f3xx-hal/pull/154
 [#152]: https://github.com/stm32-rs/stm32f3xx-hal/pull/152
@@ -333,30 +338,24 @@ let clocks = rcc
 [#101]: https://github.com/stm32-rs/stm32f3xx-hal/pull/101
 [#100]: https://github.com/stm32-rs/stm32f3xx-hal/pull/100
 [#99]: https://github.com/stm32-rs/stm32f3xx-hal/pull/99
-[#99]: https://github.com/stm32-rs/stm32f3xx-hal/pull/99
-[#99]: https://github.com/stm32-rs/stm32f3xx-hal/pull/99
 [#98]: https://github.com/stm32-rs/stm32f3xx-hal/pull/98
 [#97]: https://github.com/stm32-rs/stm32f3xx-hal/pull/97
 [#91]: https://github.com/stm32-rs/stm32f3xx-hal/pull/91
 [#86]: https://github.com/stm32-rs/stm32f3xx-hal/pull/86
-[#86]: https://github.com/stm32-rs/stm32f3xx-hal/pull/86
 [#82]: https://github.com/stm32-rs/stm32f3xx-hal/pull/82
 [#75]: https://github.com/stm32-rs/stm32f3xx-hal/pull/75
 [#72]: https://github.com/stm32-rs/stm32f3xx-hal/pull/72
 [#70]: https://github.com/stm32-rs/stm32f3xx-hal/pull/70
 [#67]: https://github.com/stm32-rs/stm32f3xx-hal/pull/67
-[#67]: https://github.com/stm32-rs/stm32f3xx-hal/pull/67
 [#60]: https://github.com/stm32-rs/stm32f3xx-hal/pull/60
 [#58]: https://github.com/stm32-rs/stm32f3xx-hal/pull/58
 [#56]: https://github.com/stm32-rs/stm32f3xx-hal/pull/56
 [#52]: https://github.com/stm32-rs/stm32f3xx-hal/pull/52
 [#50]: https://github.com/stm32-rs/stm32f3xx-hal/pull/50
-[#50]: https://github.com/stm32-rs/stm32f3xx-hal/pull/50
 [#47]: https://github.com/stm32-rs/stm32f3xx-hal/pull/47
 [#42]: https://github.com/stm32-rs/stm32f3xx-hal/pull/42
 [#39]: https://github.com/stm32-rs/stm32f3xx-hal/pull/39
 [#35]: https://github.com/stm32-rs/stm32f3xx-hal/pull/18
-[#35]: https://github.com/stm32-rs/stm32f3xx-hal/pull/35
 [#34]: https://github.com/stm32-rs/stm32f3xx-hal/pull/34
 [#33]: https://github.com/stm32-rs/stm32f3xx-hal/pull/33
 [#31]: https://github.com/stm32-rs/stm32f3xx-hal/pull/33
@@ -369,7 +368,6 @@ let clocks = rcc
 [#16]: https://github.com/stm32-rs/stm32f3xx-hal/pull/16
 [#14]: https://github.com/stm32-rs/stm32f3xx-hal/pull/14
 [#12]: https://github.com/stm32-rs/stm32f3xx-hal/pull/12
-[#12]: https://github.com/stm32-rs/stm32f3xx-hal/pull/12
 [#11]: https://github.com/stm32-rs/stm32f3xx-hal/pull/11
 [#6]: https://github.com/stm32-rs/stm32f3xx-hal/pull/6
 [#4]: https://github.com/stm32-rs/stm32f3xx-hal/pull/4

Cargo.toml

@@ -24,24 +24,22 @@ features = ["stm32f303xc", "rt", "stm32-usbd", "can"]
 targets = ["thumbv7em-none-eabihf"]
 
 [dependencies]
-cfg-if = "1.0"
+cfg-if = "1"
 cortex-m = "0.7"
 cortex-m-rt = "0.6"
 embedded-dma = "0.1"
 embedded-hal = "0.2"
-nb = "1.0"
+embedded-time = "0.10"
+nb = "1"
 paste = "1"
 rtcc = "0.2"
 stm32f3 = "0.13"
-embedded-time = "0.10"
+typenum = "1"
 
 [dependencies.embedded-hal-can]
 version = "0.1.0"
 optional = true
 
-[dependencies.bare-metal]
-version = "1.0"
-
 [dependencies.stm32-usbd]
 version = "0.6"
 optional = true
@@ -95,12 +93,12 @@ stm32f303xb = ["stm32f303", "gpio-f303", "device-selected"]
 stm32f303xc = ["stm32f303", "gpio-f303", "device-selected"]
 stm32f303xd = ["stm32f303", "gpio-f303e", "device-selected"]
 stm32f303xe = ["stm32f303", "gpio-f303e", "device-selected"]
-stm32f373 = ["gpio-f373", "stm32f3/stm32f373", "device-selected"]
-stm32f378 = ["gpio-f373", "stm32f3/stm32f373", "device-selected"]
-stm32f334 = ["gpio-f333", "stm32f3/stm32f3x4", "device-selected"]
 stm32f328 = ["gpio-f333", "stm32f3/stm32f303", "device-selected"]
 stm32f358 = ["gpio-f303", "stm32f3/stm32f303", "device-selected"]
 stm32f398 = ["gpio-f303e", "stm32f3/stm32f303", "device-selected"]
+stm32f373 = ["gpio-f373", "stm32f3/stm32f373", "device-selected"]
+stm32f378 = ["gpio-f373", "stm32f3/stm32f373", "device-selected"]
+stm32f334 = ["gpio-f333", "stm32f3/stm32f3x4", "device-selected"]
 
 defmt-default = ["defmt"]
 defmt-trace = ["defmt"]
@@ -154,6 +152,10 @@ required-features = ["stm32f303xc"]
 name = "gpio_erased"
 required-features = ["rt", "stm32f303xc"]
 
+[[example]]
+name = "gpio_interrupts"
+required-features = ["rt", "stm32f303xc"]
+
 [[test]]
 name = "rcc"
 required-features = ["rt", "defmt"]

codegen/src/codegen/gpio.rs

@@ -60,32 +60,60 @@ fn merge_pins_by_port(pins: &[gpio::Pin]) -> Result<Vec<Port>> {
 }
 
 fn gen_gpio_macro_call(ports: &[Port], feature: &str) -> Result<()> {
-    println!("gpio!([");
+    println!("gpio!({{");
+
+    gen_pac_list(ports, feature);
+
+    println!("    ports: [");
     for port in ports {
         gen_port(port, feature)?;
     }
-    println!("]);");
+    println!("    ],");
+
+    println!("}});");
     Ok(())
 }
 
+fn gen_pac_list(ports: &[Port], feature: &str) {
+    let mut pac_modules: Vec<_> = ports
+        .iter()
+        .map(|port| get_port_pac_module(port, feature))
+        .collect();
+    pac_modules.sort_unstable();
+    pac_modules.dedup();
+    println!("    pacs: [{}],", pac_modules.join(", "));
+}
+
 fn gen_port(port: &Port, feature: &str) -> Result<()> {
     let pac_module = get_port_pac_module(port, feature);
+    let port_index = match port.id {
+        'A' => 0,
+        'B' => 1,
+        'C' => 2,
+        'D' => 3,
+        'E' => 4,
+        'F' => 5,
+        'G' => 6,
+        'H' => 7,
+        _ => unreachable!(),
+    };
 
-    println!("    {{");
+    println!("        {{");
     println!(
-        "        port: ({}/{}, pac: {}),",
+        "            port: ({}/{}, {}, {}),",
         port.id,
         port.id.to_lowercase(),
+        port_index,
         pac_module,
     );
-    println!("        pins: [");
+    println!("            pins: [");
 
     for pin in &port.pins {
         gen_pin(pin)?;
     }
 
-    println!("        ],");
-    println!("    }},");
+    println!("            ],");
+    println!("        }},");
     Ok(())
 }
 
@@ -107,23 +135,19 @@ fn gen_pin(pin: &gpio::Pin) -> Result<()> {
     let af_numbers = get_pin_af_numbers(pin)?;
 
     println!(
-        "            {} => {{ reset: {}, afr: {}/{}, af: {:?} }},",
-        nr,
-        reset_mode,
-        afr,
-        afr.to_lowercase(),
-        af_numbers,
+        "                {} => {{ reset: {}, afr: {}, af: {:?} }},",
+        nr, reset_mode, afr, af_numbers,
     );
 
     Ok(())
 }
 
 fn get_pin_reset_mode(pin: &gpio::Pin) -> Result<&'static str> {
     // Debug pins default to their debug function (AF0), everything else
-    // defaults to floating input.
+    // defaults to input.
     let mode = match (pin.port()?, pin.number()?) {
-        ('A', 13) | ('A', 14) | ('A', 15) | ('B', 3) | ('B', 4) => "AF0",
-        _ => "Input<Floating>",
+        ('A', 13) | ('A', 14) | ('A', 15) | ('B', 3) | ('B', 4) => "AF0<PushPull>",
+        _ => "Input",
     };
     Ok(mode)
 }
@@ -134,7 +158,7 @@ fn get_pin_af_numbers(pin: &gpio::Pin) -> Result<Vec<u8>> {
         numbers.push(signal.af()?);
     }
 
-    numbers.sort();
+    numbers.sort_unstable();
     numbers.dedup();
 
     Ok(numbers)

examples/can.rs

@@ -38,16 +38,20 @@ fn main() -> ! {
         .freeze(&mut flash.acr);
 
     // Configure CAN RX and TX pins (AF9)
-    let can_rx = gpioa.pa11.into_af9(&mut gpioa.moder, &mut gpioa.afrh);
-    let can_tx = gpioa.pa12.into_af9(&mut gpioa.moder, &mut gpioa.afrh);
+    let rx = gpioa
+        .pa11
+        .into_af9_push_pull(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh);
+    let tx = gpioa
+        .pa12
+        .into_af9_push_pull(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh);
 
     // Initialize the CAN peripheral
-    let can = Can::new(dp.CAN, can_rx, can_tx, &mut rcc.apb1);
+    let can = Can::new(dp.CAN, rx, tx, &mut rcc.apb1);
 
     // Uncomment the following line to enable CAN interrupts
     // can.listen(Event::Fifo0Fmp);
 
-    let (mut can_tx, mut rx0, _rx1) = can.split();
+    let (mut tx, mut rx0, _rx1) = can.split();
 
     let mut led0 = gpiob
         .pb15
@@ -68,7 +72,7 @@ fn main() -> ! {
 
     let frame = CanFrame::new_data(CanId::BaseId(ID), &data);
 
-    block!(can_tx.transmit(&frame)).expect("Cannot send first CAN frame");
+    block!(tx.transmit(&frame)).expect("Cannot send first CAN frame");
 
     loop {
         let rcv_frame = block!(rx0.receive()).expect("Cannot receive CAN frame");
@@ -83,7 +87,7 @@ fn main() -> ! {
             let data: [u8; 1] = [counter];
             let frame = CanFrame::new_data(CanId::BaseId(ID), &data);
 
-            block!(can_tx.transmit(&frame)).expect("Cannot send CAN frame");
+            block!(tx.transmit(&frame)).expect("Cannot send CAN frame");
         }
 
         iwdg.feed();

examples/gpio_erased.rs

@@ -9,7 +9,7 @@ use cortex_m::asm;
 use cortex_m_rt::entry;
 use cortex_m_semihosting::hprintln;
 
-use hal::gpio::{self, Floating, Input};
+use hal::gpio::{self, Input};
 use hal::pac;
 use hal::prelude::*;
 use stm32f3xx_hal as hal;
@@ -23,7 +23,7 @@ fn main() -> ! {
     let mut gpioc = dp.GPIOC.split(&mut rcc.ahb);
     let mut gpiod = dp.GPIOD.split(&mut rcc.ahb);
 
-    let mut pin_array: [gpio::PXx<Input<Floating>>; 4] = [
+    let mut pin_array: [gpio::PXx<Input>; 4] = [
         gpiob
             .pb11
             .into_floating_input(&mut gpiob.moder, &mut gpiob.pupdr)