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Commit 2811a92

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Update more code for new pac
1 parent c813ea1 commit 2811a92

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testsuite/tests/adc.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -59,12 +59,12 @@ mod tests {
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6060
// This is a workaround, so that the debugger will not disconnect imidiatly on asm::wfi();
6161
// https://github.com/probe-rs/probe-rs/issues/350#issuecomment-740550519
62-
dp.DBGMCU.cr.modify(|_, w| {
62+
dp.DBGMCU.cr().modify(|_, w| {
6363
w.dbg_sleep().set_bit();
6464
w.dbg_standby().set_bit();
6565
w.dbg_stop().set_bit()
6666
});
67-
dp.RCC.ahbenr.modify(|_, w| w.dma1en().enabled());
67+
dp.RCC.ahbenr().modify(|_, w| w.dma1en().enabled());
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6969
let mut rcc = dp.RCC.constrain();
7070
let mut flash = dp.FLASH.constrain();
@@ -79,12 +79,12 @@ mod tests {
7979
// Slow down ADC
8080
unsafe {
8181
(*pac::RCC::ptr())
82-
.cfgr2
83-
.modify(|_, w| w.adc12pres().variant(pac::rcc::cfgr2::ADC12PRES_A::Div64))
82+
.cfgr2()
83+
.modify(|_, w| w.adc12pres().variant(pac::rcc::cfgr2::ADC12PRES::Div64))
8484
};
8585
dp.ADC1_2
86-
.ccr
87-
.modify(|_, w| w.ckmode().variant(pac::adc1_2::ccr::CKMODE_A::Asynchronous));
86+
.ccr()
87+
.modify(|_, w| w.ckmode().variant(pac::adc1_2::ccr::CKMODE::Asynchronous));
8888
let mut common_adc = CommonAdc::new(dp.ADC1_2, &clocks, &mut rcc.ahb);
8989

9090
defmt::info!(
@@ -393,9 +393,9 @@ fn ADC1_2() {
393393
// SAFETY: Mutable access to the ADC1_2 peripheral, while knowing that
394394
// no-one can pre-empt the interrupt.
395395
let (eos, eoc) = unsafe {
396-
let isr = &(*pac::ADC1::ptr()).isr.read();
396+
let isr = &(*pac::ADC1::ptr()).isr().read();
397397
(*pac::ADC1::ptr())
398-
.isr
398+
.isr()
399399
.modify(|_, w| w.eos().clear().eoc().clear());
400400
(isr.eos(), isr.eoc())
401401
};

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