@@ -1472,7 +1472,7 @@ macro_rules! adc_common {
14721472 }
14731473
14741474 fn clock( & self , clocks: & Clocks ) -> Option <Hertz > {
1475- use crate :: pac:: rcc:: cfgr2:: ADC12PRES ;
1475+ use crate :: pac:: rcc:: cfgr2:: ADC1PRES ;
14761476 use crate :: pac:: RCC ;
14771477 // SAFETY: atomic read with no side effects
14781478 let adc_pres = unsafe { & ( * RCC :: ptr( ) ) . cfgr2( ) . read( ) . $adcXYpres( ) } ;
@@ -1485,19 +1485,19 @@ macro_rules! adc_common {
14851485 Some ( pllclk) if !adc_pres. is_no_clock( ) => {
14861486 pllclk
14871487 / match adc_pres. variant( ) {
1488- Some ( ADC12PRES :: Div1 ) => 1 ,
1489- Some ( ADC12PRES :: Div2 ) => 2 ,
1490- Some ( ADC12PRES :: Div4 ) => 4 ,
1491- Some ( ADC12PRES :: Div6 ) => 6 ,
1492- Some ( ADC12PRES :: Div8 ) => 8 ,
1493- Some ( ADC12PRES :: Div10 ) => 10 ,
1494- Some ( ADC12PRES :: Div12 ) => 12 ,
1495- Some ( ADC12PRES :: Div16 ) => 16 ,
1496- Some ( ADC12PRES :: Div32 ) => 32 ,
1497- Some ( ADC12PRES :: Div64 ) => 64 ,
1498- Some ( ADC12PRES :: Div128 ) => 128 ,
1499- Some ( ADC12PRES :: Div256 ) => 256 ,
1500- Some ( ADC12PRES :: NoClock ) | None => 1 ,
1488+ Some ( ADC1PRES :: Div1 ) => 1 ,
1489+ Some ( ADC1PRES :: Div2 ) => 2 ,
1490+ Some ( ADC1PRES :: Div4 ) => 4 ,
1491+ Some ( ADC1PRES :: Div6 ) => 6 ,
1492+ Some ( ADC1PRES :: Div8 ) => 8 ,
1493+ Some ( ADC1PRES :: Div10 ) => 10 ,
1494+ Some ( ADC1PRES :: Div12 ) => 12 ,
1495+ Some ( ADC1PRES :: Div16 ) => 16 ,
1496+ Some ( ADC1PRES :: Div32 ) => 32 ,
1497+ Some ( ADC1PRES :: Div64 ) => 64 ,
1498+ Some ( ADC1PRES :: Div128 ) => 128 ,
1499+ Some ( ADC1PRES :: Div256 ) => 256 ,
1500+ Some ( ADC1PRES :: NoClock ) | None => 1 ,
15011501 }
15021502 }
15031503 _ => {
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