@@ -1472,7 +1472,7 @@ macro_rules! adc_common {
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}
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fn clock( & self , clocks: & Clocks ) -> Option <Hertz > {
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- use crate :: pac:: rcc:: cfgr2:: ADC12PRES ;
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+ use crate :: pac:: rcc:: cfgr2:: ADC1PRES ;
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use crate :: pac:: RCC ;
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// SAFETY: atomic read with no side effects
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let adc_pres = unsafe { & ( * RCC :: ptr( ) ) . cfgr2( ) . read( ) . $adcXYpres( ) } ;
@@ -1485,19 +1485,19 @@ macro_rules! adc_common {
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Some ( pllclk) if !adc_pres. is_no_clock( ) => {
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pllclk
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/ match adc_pres. variant( ) {
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- Some ( ADC12PRES :: Div1 ) => 1 ,
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- Some ( ADC12PRES :: Div2 ) => 2 ,
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- Some ( ADC12PRES :: Div4 ) => 4 ,
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- Some ( ADC12PRES :: Div6 ) => 6 ,
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- Some ( ADC12PRES :: Div8 ) => 8 ,
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- Some ( ADC12PRES :: Div10 ) => 10 ,
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- Some ( ADC12PRES :: Div12 ) => 12 ,
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- Some ( ADC12PRES :: Div16 ) => 16 ,
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- Some ( ADC12PRES :: Div32 ) => 32 ,
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- Some ( ADC12PRES :: Div64 ) => 64 ,
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- Some ( ADC12PRES :: Div128 ) => 128 ,
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- Some ( ADC12PRES :: Div256 ) => 256 ,
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- Some ( ADC12PRES :: NoClock ) | None => 1 ,
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+ Some ( ADC1PRES :: Div1 ) => 1 ,
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+ Some ( ADC1PRES :: Div2 ) => 2 ,
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+ Some ( ADC1PRES :: Div4 ) => 4 ,
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+ Some ( ADC1PRES :: Div6 ) => 6 ,
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+ Some ( ADC1PRES :: Div8 ) => 8 ,
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+ Some ( ADC1PRES :: Div10 ) => 10 ,
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+ Some ( ADC1PRES :: Div12 ) => 12 ,
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+ Some ( ADC1PRES :: Div16 ) => 16 ,
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+ Some ( ADC1PRES :: Div32 ) => 32 ,
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+ Some ( ADC1PRES :: Div64 ) => 64 ,
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+ Some ( ADC1PRES :: Div128 ) => 128 ,
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+ Some ( ADC1PRES :: Div256 ) => 256 ,
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+ Some ( ADC1PRES :: NoClock ) | None => 1 ,
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}
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}
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_ => {
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