Make HSI public and Hertz

Author: Sh3Rm4n

src/i2c.rs

@@ -132,15 +132,15 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
         // t_SCL ~= t_SYNC1 + t_SYNC2 + t_SCLL + t_SCLH
         let i2cclk = I2C::clock(&clocks).0;
         let ratio = i2cclk / freq.integer() - 4;
-        let (presc, scll, sclh, sdadel, scldel) = if freq.integer() >= 100_000 {
+        let (presc, scll, sclh, sdadel, scldel) = if freq >= 100.kHz() {
             // fast-mode or fast-mode plus
             // here we pick SCLL + 1 = 2 * (SCLH + 1)
             let presc = ratio / 387;
 
             let sclh = ((ratio / (presc + 1)) - 3) / 3;
             let scll = 2 * (sclh + 1) - 1;
 
-            let (sdadel, scldel) = if freq.integer() > 400_000 {
+            let (sdadel, scldel) = if freq > 400.kHz() {
                 // fast-mode plus
                 let sdadel = 0;
                 let scldel = i2cclk / 4_000_000 / (presc + 1) - 1;
@@ -449,7 +449,7 @@ macro_rules! i2c {
                 fn clock(clocks: &Clocks) -> Hertz {
                     // NOTE(unsafe) atomic read with no side effects
                     match unsafe { (*RCC::ptr()).cfgr3.read().$i2cXsw().variant() } {
-                        I2C1SW_A::HSI => Hertz(8_000_000),
+                        I2C1SW_A::HSI => crate::rcc::HSI,
                         I2C1SW_A::SYSCLK => clocks.sysclk(),
                     }
                 }

src/rcc.rs

@@ -182,7 +182,10 @@ impl APB2 {
     }
 }
 
-const HSI: u32 = 8_000_000; // Hz
+/// Frequency of interal hardware RC oscillator (HSI OSC)
+pub const HSI: Hertz = Hertz(8_000_000);
+/// Frequency of external 32.768 kHz oscillator (LSE OSC)
+pub const LSE: Hertz = Hertz(32_768);
 
 // some microcontrollers do not have USB
 #[cfg(any(feature = "stm32f301", feature = "stm32f318", feature = "stm32f334",))]
@@ -469,7 +472,7 @@ impl CFGR {
         feature = "stm32f398"
     )))]
     fn calc_pll(&self, sysclk: u32) -> (u32, PllConfig) {
-        let pllsrcclk = self.hse.unwrap_or(HSI / 2);
+        let pllsrcclk = self.hse.unwrap_or(HSI.integer() / 2);
         // Get the optimal value for the pll divisor (PLL_DIV) and multiplier (PLL_MUL)
         // Only for HSE PLL_DIV can be changed
         let (pll_mul, pll_div): (u32, Option<u32>) = if self.hse.is_some() {
@@ -545,7 +548,7 @@ impl CFGR {
         feature = "stm32f398",
     ))]
     fn calc_pll(&self, sysclk: u32) -> (u32, PllConfig) {
-        let pllsrcclk = self.hse.unwrap_or(HSI);
+        let pllsrcclk = self.hse.unwrap_or(HSI.integer());
 
         let (pll_mul, pll_div) = {
             // Get the optimal value for the pll divisor (PLL_DIV) and multiplcator (PLL_MUL)
@@ -613,15 +616,17 @@ impl CFGR {
             // Oscillator (max 32 Mhz), without using the PLL.
             (Some(sysclk), Some(hse)) if sysclk == hse => (hse, cfgr::SW_A::HSE, None),
             // No need to use the PLL
-            (Some(sysclk), None) if sysclk == HSI => (HSI, cfgr::SW_A::HSI, None),
+            (Some(sysclk), None) if sysclk == HSI.integer() => {
+                (HSI.integer(), cfgr::SW_A::HSI, None)
+            }
             (Some(sysclk), _) => {
                 let (sysclk, pll_config) = self.calc_pll(sysclk);
                 (sysclk, cfgr::SW_A::PLL, Some(pll_config))
             }
             // Use HSE as system clock
             (None, Some(hse)) => (hse, cfgr::SW_A::HSE, None),
             // Use HSI as system clock
-            (None, None) => (HSI, cfgr::SW_A::HSI, None),
+            (None, None) => (HSI.integer(), cfgr::SW_A::HSI, None),
         }
     }