Merge pull request #35 from Sh3Rm4n/spi-fix

Fix spi initialization

Author: Sh3Rm4n

CHANGELOG.md

@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   - This allow using 72 MHz `sysclk` on the `stm32f303`
 - Analog gpio trait ([#33](https://github.com/stm32-rs/stm32f3xx-hal/pull/33))
 - Add PWM Channels ([#34](https://github.com/stm32-rs/stm32f3xx-hal/pull/34))
+- SPI embedded hal modes are now public ([#35](https://github.com/stm32-rs/stm32f3xx-hal/pull/18))
 
 ### Breaking changes
 
@@ -24,6 +25,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - `stm32f303` is now split into `stm32f303xd` and `stm32f303xe` as they provide
   different alternate gpio functions. `stm32f303` is still available.
 
+### Fixed
+
+- Fixed wrong initialization of the SPI ([#35](https://github.com/stm32-rs/stm32f3xx-hal/pull/18))
 
 ## [v0.3.0] - 2019-08-26
 

Cargo.toml

@@ -86,3 +86,7 @@ required-features = ["rt", "stm32f303xc"]
 [[example]]
 name = "usb_serial"
 required-features = ["rt", "stm32f303xc", "stm32-usbd"]
+
+[[example]]
+name = "spi"
+required-features = ["stm32f303"]

examples/spi.rs

@@ -0,0 +1,65 @@
+//! Example of configuring spi.
+//! Target board: STM32F3DISCOVERY
+#![no_std]
+#![no_main]
+
+extern crate panic_semihosting;
+
+use stm32f3xx_hal as hal;
+
+use cortex_m_rt::entry;
+
+use hal::prelude::*;
+use hal::spi::{Mode, Phase, Polarity, Spi};
+use hal::stm32;
+
+#[entry]
+fn main() -> ! {
+    let dp = stm32::Peripherals::take().unwrap();
+
+    let mut flash = dp.FLASH.constrain();
+    let mut rcc = dp.RCC.constrain();
+    let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
+
+    let clocks = rcc
+        .cfgr
+        .use_hse(8.mhz())
+        .sysclk(48.mhz())
+        .pclk1(24.mhz())
+        .freeze(&mut flash.acr);
+
+    // Configure pins for SPI
+    let sck = gpioa.pa5.into_af5(&mut gpioa.moder, &mut gpioa.afrl);
+    let miso = gpioa.pa6.into_af5(&mut gpioa.moder, &mut gpioa.afrl);
+    let mosi = gpioa.pa7.into_af5(&mut gpioa.moder, &mut gpioa.afrl);
+
+    let spi_mode = Mode {
+        polarity: Polarity::IdleLow,
+        phase: Phase::CaptureOnFirstTransition,
+    };
+
+    let mut spi = Spi::spi1(
+        dp.SPI1,
+        (sck, miso, mosi),
+        spi_mode,
+        3.mhz(),
+        clocks,
+        &mut rcc.apb2,
+    );
+
+    // Create an `u8` array, which can be transfered via SPI.
+    let msg_send: [u8; 8] = [0xD, 0xE, 0xA, 0xD, 0xB, 0xE, 0xE, 0xF];
+    // Clone the array, as it would be mutually shared in `transfer` while simultaniously would be
+    // immutable shared in `assert_eq`.
+    let mut msg_sending = msg_send.clone();
+    // Transfer the content of the array via SPI and receive it's output.
+    // When MOSI and MISO pins are connected together, `msg_received` should receive the content.
+    // from `msg_sending`
+    let msg_received = spi.transfer(&mut msg_sending).unwrap();
+
+    // Check, if msg_send and msg_received are identical.
+    // This succeeds, when master and slave of the SPI are connected.
+    assert_eq!(msg_send, msg_received);
+
+    loop {}
+}

src/spi.rs

@@ -2,7 +2,8 @@
 
 use core::ptr;
 
-use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
+use crate::hal::spi::FullDuplex;
+pub use crate::hal::spi::{Mode, Phase, Polarity};
 use crate::stm32::{SPI1, SPI2, SPI3};
 use nb;
 
@@ -175,13 +176,9 @@ macro_rules! hal {
                             .bit(mode.polarity == Polarity::IdleHigh)
                             .mstr()
                             .set_bit()
-                            .br();
-
-                        unsafe {
-                            w.bits(br);
-                        }
-
-                        w.spe()
+                            .br()
+                            .bits(br)
+                            .spe()
                             .set_bit()
                             .lsbfirst()
                             .clear_bit()